Sharp LC-39LE751EK (serv.man3) Service Manual ▷ View online
49
LC-39/50LE750
LC-39/50LE751
LC-39/50LE752
Sub channel mix into left and right channels.
Selectable high- or low-bandwidth noise-shaping topologies.
Selectable clock input ratio.
96-kHz internal processing sample rate.
Thermal overload and short-circuit protection technology
Video apps: 576 x fs input mode supported.
IC 2702: Headphone Amplifier.
Part number: TS488IQT (ST MICRO)
Sharp code : RH-IXD542WJZZY.
Part number: TS488IQT (ST MICRO)
Sharp code : RH-IXD542WJZZY.
http://www.st.com/st-web-ui/static/active/en/resource/technical/document/datasheet/CD00083715.pdf
Ω
Ω
Ω
Features:
Pop and click noise protection circuitry.
Operating range from VCC = 2.2 V to 5.5 V.
Standby mode active low (TS488) or high (TS489).
Output power:
– 120 mW at 5 V, into 16 Ω with 0.1% THD+N max (1 kHz).
– 55 mW at 3.3 V, into 16 Ω with 0.1% THD+N max (1 kHz).
– 120 mW at 5 V, into 16 Ω with 0.1% THD+N max (1 kHz).
– 55 mW at 3.3 V, into 16 Ω with 0.1% THD+N max (1 kHz).
Low current consumption: 2.7 mA max at 5 V.
Ultra-low standby current consumption: 10 nA typical.
High signal-to-noise ratio.
High crosstalk immunity: 102 dB (F = 1 kHz).
PSRR: 70 dB typ. (F = 1 kHz), inputs grounded at 5 V.
Unity-gain stable.
Short-circuit protection circuitry.
IC9552: USB 2.0 Hi-Speed Hub Controller
Part number: USB2514B-AEZG (SMSC)
Sharp code: VHI2514BAEZ-1Q
Part number: USB2514B-AEZG (SMSC)
Sharp code: VHI2514BAEZ-1Q
http://www.smsc.com/Downloads/SMSC/Downloads_Public/Data_Sheets/251xb.pdf
The SMSC USB251x hub is a family of low-power, OEM
configurable, MTT (multi transaction translator) 1 hub controller
IC products for embedded USB solutions. The “x” in the part
number indicates the number of downstream ports available. The
SMSC hub supports low-speed, full-speed, and hi-speed (if
operating as a hi-speed hub) downstream devices on all of the
enabled downstream ports.
Features
Full power management with individual or ganged power
control of each downstream port.
control of each downstream port.
Fully integrated USB termination and pull-up/pull-down
resistors.
resistors.
Supports a single external 3.3 V supply source; internal
regulators provide 1.2 V or 1.8 V internal core voltage.
regulators provide 1.2 V or 1.8 V internal core voltage.
On-chip driver for 24 MHz crystal resonator or external 24/48
MHz clock input.
MHz clock input.
Customizable vendor ID, product ID, and device ID.
ESD protection up to 4 kilovolts on all USB pins.
Supports self- or bus-powered operation.
USB251xB2 and USB251xBi products support the USB Battery Charging specification.
Package: 36-pin QFN (6x6 mm).
MAJOR ICs INFORMATION ( continued )
50
LC-39/50LE750
LC-39/50LE751
LC-39/50LE752
IC 3501, IC3502 & IC 3503: 2Gb 16Bits DDR3-1600 SDRAM
Part number: MT41J128M16JT-125:K (MICRON)
Sharp code: RH-IXD538WJZZQ
Part number: MT41J128M16JT-125:K (MICRON)
Sharp code: RH-IXD538WJZZQ
http://www.micron.com/~/media/Documents/Products/Data%20Sheet/DRAM/2Gb_DDR3_SDRAM.pdf
DDR3 SDRAM uses double data rate architecture to achieve high-speed operation. The double data rate architecture is an 8n-
prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write
operation for the DDR3 SDRAM effectively consists of a single 8n-bit-wide, four-clock cycle data transfer at the internal
DRAM core and eight corresponding n-bit-wide, one half-clock-cycle data transfers at the I/O pins. The differential data strobe
(DQS, DQS#) is transmitted externally, along with data, for use in data capture at the DDR3 SDRAM input receiver. DQS is
center-aligned with data for WRITEs. The read data is transmitted by the DDR3 SDRAM and edge-aligned to the data strobes.
The DDR3 SDRAM operates from a differential clock (CK and CK#). The crossing of CK going HIGH and CK# going LOW is
referred to as the positive edge of CK. Control, command, and address signals are registered at every positive edge of CK. Input
data is registered on the first rising edge of DQS after the WRITE preamble, and output data is referenced on the first rising edge
of DQS after the READ preamble.
Read and write accesses to the DDR3 SDRAM are burst-oriented. Accesses start at a selected location and continue for a
programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVATE command,
which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVATE command
are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE commands
are used to select the bank and the starting column location for the burst access.
The device uses a READ and WRITE BL8 and BC4. An auto precharge function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst access.
As with standard DDR SDRAM, the pipelined, multibank architecture of DDR3 SDRAM allows for concurrent operation,
thereby providing high bandwidth by hiding row precharge and activation time.
A self refresh mode is provided, along with a power-saving, power-down mode.
Features:
prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write
operation for the DDR3 SDRAM effectively consists of a single 8n-bit-wide, four-clock cycle data transfer at the internal
DRAM core and eight corresponding n-bit-wide, one half-clock-cycle data transfers at the I/O pins. The differential data strobe
(DQS, DQS#) is transmitted externally, along with data, for use in data capture at the DDR3 SDRAM input receiver. DQS is
center-aligned with data for WRITEs. The read data is transmitted by the DDR3 SDRAM and edge-aligned to the data strobes.
The DDR3 SDRAM operates from a differential clock (CK and CK#). The crossing of CK going HIGH and CK# going LOW is
referred to as the positive edge of CK. Control, command, and address signals are registered at every positive edge of CK. Input
data is registered on the first rising edge of DQS after the WRITE preamble, and output data is referenced on the first rising edge
of DQS after the READ preamble.
Read and write accesses to the DDR3 SDRAM are burst-oriented. Accesses start at a selected location and continue for a
programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVATE command,
which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVATE command
are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE commands
are used to select the bank and the starting column location for the burst access.
The device uses a READ and WRITE BL8 and BC4. An auto precharge function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst access.
As with standard DDR SDRAM, the pipelined, multibank architecture of DDR3 SDRAM allows for concurrent operation,
thereby providing high bandwidth by hiding row precharge and activation time.
A self refresh mode is provided, along with a power-saving, power-down mode.
Features:
VDD = VDDQ = 1.5V ±0.075V. 1.5V center-terminated push/pull I/O.
Differential bidirectional data strobe with 8n-bit prefetch architecture.
Differential clock inputs (CK, CK#).
8 internal banks.
Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals.
Programmable CAS READ latency (CL). Posted CAS additive latency (AL).
Programmable CAS WRITE latency (CWL) based on tCK.
Fixed burst length (BL) of 8 and burst chop (BC) of 4 (via the mode register set [MRS]).
Self refresh temperature (SRT).
Multipurpose register with Output driver calibration.
MAJOR ICs INFORMATION ( continued )
51
LC-39/50LE750
LC-39/50LE751
LC-39/50LE752
IC9551: Adjustable Current Limited Load Switch with Fault Flag (USB1).
Part number: AAT4614IGU-2-T1 (SKYWORKS INC.)
Sharp code: RH-IXD309WJZZY
Part number: AAT4614IGU-2-T1 (SKYWORKS INC.)
Sharp code: RH-IXD309WJZZY
http://www.skyworksinc.com/uploads/documents/201939A.pdf
The AAT4614 Smart Switch is a current limited P-channel MOSFET power switch designed for high side load switching
applications. This switch operates with inputs ranging from 2.4V to 5.5V, making it ideal for both 3V and 5V systems. An
integrated current-limiting circuit protects the input supply against large currents which may cause the supply to fall out of
regulation. Reverse current blocking is provided to protect the load switch from reverse current potentials while the device is
shutdown.
The AAT4614 is also protected from thermal overload which is limited by power dissipation and junction temperatures. Current
limit threshold is programmed with a resistor from SET to ground and may be adjusted for levels up to 1.4A. The ultra-fast
current limit response to a sudden short circuit is a mere 1
applications. This switch operates with inputs ranging from 2.4V to 5.5V, making it ideal for both 3V and 5V systems. An
integrated current-limiting circuit protects the input supply against large currents which may cause the supply to fall out of
regulation. Reverse current blocking is provided to protect the load switch from reverse current potentials while the device is
shutdown.
The AAT4614 is also protected from thermal overload which is limited by power dissipation and junction temperatures. Current
limit threshold is programmed with a resistor from SET to ground and may be adjusted for levels up to 1.4A. The ultra-fast
current limit response to a sudden short circuit is a mere 1
μs which reduces the requirements of local supply bypassing. An open
drain FAULT flag signals an over-current or over-temperature condition after a 4ms blanking time to prevent false reporting.
Quiescent current is a low 10
Quiescent current is a low 10
μA and the supply current decreases to less than 1μA in shutdown mode.
The AAT4614 is offered in the 8-pin SC70JW, SOT23-6 and SOT23-5 packages, and is specified for operation over the -40°C to
+85°C ambient temperature range.
+85°C ambient temperature range.
Features.
Input Voltage Range: 2.4V to 5.5V.
Programmable Over-Current Threshold.
Fast Transient Response:
1μs Response to Short Circuit.
10μA Typical while Enabled.
160mΩ Typical R
DS(ON).
Only 2.4V Needed for ON/OFF Control.
Under-Voltage Lockout.
Reverse Blocking During Disable.
4ms Fault Blanking.
Fault Flag Open Drain Output.
Active Hi/Lo Enable Options.
Over-Temperature Protection.
IC9553: Low Dropout LDO (USB2)
Part number: S-1170B50UC-OUJTFG (SEIKO)
Sharp code: VHIS170B50U-1Y
http://datasheet.sii-ic.com/en/voltage_regulator/S1170_E.pdf
The S-1170 Series is a positive voltage regulator with a low dropout voltage (LDO), high output voltage accuracy, and low
current consumption developed based on CMOS technology.
A built-in low on-resistance transistor provides a low dropout voltage and large output current, a built-in overcurrent protector
prevents the load current from exceeding the current capacitance of the output transistor, and a built-in thermal shutdown circuit
prevents damage caused by the heat. An ON/OFF circuit ensures a long battery life. Compared with the voltage regulators using
the conventional CMOS process, a larger variety of capacitors are available, including small ceramic capacitors. Small SOT-89-
5 and 6-Pin HSON(A) packages realize high-density mounting.
Features:
Output voltage: 1.5 V to 5.5 V, selectable in 0.1 V steps.
High-accuracy output voltage: ±1.0%.
Low dropout voltage (LDO): 120 mV typ. (3.0 V output
product, Iout =300 mA).
product, Iout =300 mA).
Low current consumption: During operation 80 μA typ.
160 μA max., During shutdown 0.1 μA typ. 1.0 μA max.
160 μA max., During shutdown 0.1 μA typ. 1.0 μA max.
High peak current capability: 800 mA output is possible
(@ Vin >Vout(S) +1.0 V) *1
(@ Vin >Vout(S) +1.0 V) *1
Built-in ON/OFF circuit.
High ripple rejection: 70 dB typ. (@ 1.0 kHz)
Built-in overcurrent protector: Overcurrent of output
transistor can be restricted.
transistor can be restricted.
Built-in thermal shutdown circuit.
MAJOR ICs INFORMATION ( continued )
52
LC-39/50LE750
LC-39/50LE751
LC-39/50LE752
IC 3301: SOC Freeman Premier 2
Part number: FLI7560-AAB (ST MICRO)
Sharp code: RH-IXD514WJZZQ
Part number: FLI7560-AAB (ST MICRO)
Sharp code: RH-IXD514WJZZQ
http://www.st.com/st-web-ui/static/active/en/resource/technical/document/data_brief/DM00063486.pdf
The FLI7560 is a revolutionary new iDTV SoC that integrates two highly successful, market proven subsystems: STi710x
digital/front-end processing and multi-format audio/video decoding from the STB market, and Faroudja video/back-end
processing from the TV market. The FLI7560 is a high-performance, state-of-the-art SoC that can power
DTT/cable/satellite/IPTV iDTV designs for worldwide deployment. From the software compatibility extending from the mature
STi710x STAPI layer to the extensive video processing, tuning, and tools from Faroudja Labs, FLI7560 is an ideal solution for
addressing the next generation of iDTV design requirements.
The FLI7560 is the latest in a family of scalable performance and software-compatible H.264 SoCs that address mainstream and
performance segments of the iDTV market. Notably, it is a single-chip, 120 Hz TV solution incorporating Motion-Corrected
Temporal Interpolation (MCTi) Faroudja technology. It utilizes industry-leading vector estimation to interpolate in between
frames to correct film motion judder and panel motion blurring. Combining the artistic elements of film with the linear motion of
video, FLI7560 provides audiences with a uniquely enjoyable viewing experience.
FLI7560 implements the latest generation of Faroudja Video Optimized technologies, which allow a high degree of
customization for TV OEMs. Key technology improvements in this area include 14-bit color and contrast processing, upgraded
sharpness, upgraded temporal noise reduction, and new MPEG noise reduction. Furthermore, FLI7560 supports all connectivity
requirements to 3D sources and all mandatory 3D formats defined in the HDMI 1.4b specification.
Along with its high performance CPU, the FLI7560 is equipped with 256 Kbyte of level 2 cache to deliver the smoothest multi-
instance Connected TV intuitive user experience. In addition, with its A/V decode, graphics engine, motion judder reduction and
motion blur removal features, and extensive network interface capability, FLI7560 enables 3DTVs to deliver rich applications
for convenient access to multimedia content, both from within the home, as well as from the web.
digital/front-end processing and multi-format audio/video decoding from the STB market, and Faroudja video/back-end
processing from the TV market. The FLI7560 is a high-performance, state-of-the-art SoC that can power
DTT/cable/satellite/IPTV iDTV designs for worldwide deployment. From the software compatibility extending from the mature
STi710x STAPI layer to the extensive video processing, tuning, and tools from Faroudja Labs, FLI7560 is an ideal solution for
addressing the next generation of iDTV design requirements.
The FLI7560 is the latest in a family of scalable performance and software-compatible H.264 SoCs that address mainstream and
performance segments of the iDTV market. Notably, it is a single-chip, 120 Hz TV solution incorporating Motion-Corrected
Temporal Interpolation (MCTi) Faroudja technology. It utilizes industry-leading vector estimation to interpolate in between
frames to correct film motion judder and panel motion blurring. Combining the artistic elements of film with the linear motion of
video, FLI7560 provides audiences with a uniquely enjoyable viewing experience.
FLI7560 implements the latest generation of Faroudja Video Optimized technologies, which allow a high degree of
customization for TV OEMs. Key technology improvements in this area include 14-bit color and contrast processing, upgraded
sharpness, upgraded temporal noise reduction, and new MPEG noise reduction. Furthermore, FLI7560 supports all connectivity
requirements to 3D sources and all mandatory 3D formats defined in the HDMI 1.4b specification.
Along with its high performance CPU, the FLI7560 is equipped with 256 Kbyte of level 2 cache to deliver the smoothest multi-
instance Connected TV intuitive user experience. In addition, with its A/V decode, graphics engine, motion judder reduction and
motion blur removal features, and extensive network interface capability, FLI7560 enables 3DTVs to deliver rich applications
for convenient access to multimedia content, both from within the home, as well as from the web.
Features
ST231@450MHz for advanced HD video decoding (H.264/VC-1/MPEG2/…).
ÆWorldwide DTT broadcast video standards.
Dual ST231@450MHz for advanced multichannel audio decoding (MPEG-1/2, MP3, WMA, Dolby® Digital/Dolby Digital+,
AAC/AAC+/…)
AAC/AAC+/…)
Æ Worldwide DTT broadcast audio standards.
Dual ST40 CPU@450MHz (delivers 1600+DMIPS) runs Linux and OS21
Æ One CPU fully dedicated to application and user interface.
256 Kbyte level 2 cache --> For high performance Internet TV applications.
Faroudja® video processing for Main Video --> Vivid picture quality for the consumer.
Full support for HDMI 1.4b mandatory 3DTV input formats.
Horizontal/vertical image flip support all panel types.
Faroudja MCTi™ Frame Rate Conversion (FRC) for 2D and 3D content (film and video).
Higher performance for SMART TV with more responsive navigation.
3DTV support 120 Hz (line-interleaved) and 60L60R (frame-sequential).
Integrates auto 2D to 3D video/text conversion and depth control.
Worldwide analog audio demodulator.
14-bit Advanced Color Management (3D) and Contrast processing --> Ultimate video quality for OEMs and consumers.
High-quality graphics for rich, easy-to-use GUI.
Advanced security supporting embedded CA, CI/CI+ and DRM apps; copy protection support including HDCP, AES/DES/TDES,
RoviTM.
RoviTM.
48-bit (3 x 16 or 1 x 16 + 1 x 32) DDR2/DDR31066 Mbps DRAM I/F --> Performance and flexibility with DRAM ICs.
Quad high-speed 10-bit LVDS outputs --> convenient connectivity to panel TCON.
MAJOR ICs INFORMATION ( continued )
Click on the first or last page to see other LC-39LE751EK (serv.man3) service manuals if exist.