Sharp LC-37GA5E (serv.man17) Service Manual ▷ View online
85
LC-26GA5E
LC-32GA5E
LC-32GA5E
LC-37GA5E
3. IC2201 (RH-IXB372WJZZ)
3.1. Pinning IC2201
Figure 2-1 Pin Locations
157
208
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
116
117
118
119
120
121
122
123
124
125
115
126
127
129
130
131
132
133
134
135
136
137
138
128
139
140
142
143
144
145
146
147
148
149
150
151
141
152
153
154
155
156
158
159
160
161
162
163
164
165
166
159
160
161
162
163
164
165
166
173
174
175
176
177
178
174
175
176
177
178
167
168
169
170
171
172
168
169
170
171
172
179
180
180
187
188
189
190
191
192
188
189
190
191
192
181
182
183
184
185
186
182
183
184
185
186
193
194
194
201
202
203
204
205
206
202
203
204
205
206
195
196
197
198
199
200
196
197
198
199
200
207
PW1306
(Top View)
DV
DD
1
DG
N
D
1
DV
DD
1
DG
N
D
1
NC
AV
DD
NC
NC
AG
N
D
NC
NC
AG
N
D
NC
NC
AG
N
D
NC
NC
AV
DD
DG
N
D
1
DV
DD
1
PG
N
D
PV
D
FI
LT
PV
D
PG
N
D
PV
D
PG
N
D
AL
V
D
D
AL
V
D
D
AL
G
N
D
AL
G
N
D
AV
DD
AV
DD
AG
N
D
AG
N
D
AV
DD
RA
IN
AG
N
D
AV
DD
AG
N
D
AV
DD
AG
N
D
GA
IN
S
OGIN
AG
N
D
AV
DD
AG
N
D
AV
DD
AG
N
D
BA
IN
AG
N
D
AV
DD
VDDQ3
DEN
DHS
DVS
DOB6
DOB7
DER0
DER1
VSS
VDD1
DER2
DER3
DER4
DER5
DER6
DER7
DEG0
DEG1
DEG2
DEG3
VSSQ
VDDQ3
DEG4
DEG5
DEG6
DEG7
DEB0
DEB1
VSS
VDD1
DEB2
DEB3
VCLK
DEB4
DEB5
VSSQ
VDDQ3
DEB6
DEB7
HSYNC
VSYNC
PORTD0
PORTD1
PORTD2
PORTD3
PORTD4
PORTD5
PORTD6
PORTD7
VPEN
TXD
RXD
DEN
DHS
DVS
DOB6
DOB7
DER0
DER1
VSS
VDD1
DER2
DER3
DER4
DER5
DER6
DER7
DEG0
DEG1
DEG2
DEG3
VSSQ
VDDQ3
DEG4
DEG5
DEG6
DEG7
DEB0
DEB1
VSS
VDD1
DEB2
DEB3
VCLK
DEB4
DEB5
VSSQ
VDDQ3
DEB6
DEB7
HSYNC
VSYNC
PORTD0
PORTD1
PORTD2
PORTD3
PORTD4
PORTD5
PORTD6
PORTD7
VPEN
TXD
RXD
D4
D5
D6
D7
D8
D9
D1
0
D1
1
D1
2
VS
S
VD
D
1
D1
3
D1
4
D1
5
NC
NC
NC
NC
NC
TE
S
T
E
N
VS
S
VD
D
1
VS
SQ
VD
D
Q
3
RE
S
E
T
_
N
DO
R
0
DO
R
1
DO
R
2
DO
R
3
DO
R
4
DO
R
5
DO
R
6
DO
R
7
VS
SQ
VD
D
Q
3
D
OG0
D
OG1
D
OG2
D
OG3
D
OG4
D
OG5
D
OG6
D
OG7
DO
B
0
DO
B
1
DO
B
2
DO
B
3
DO
B
4
DO
B
5
DC
L
K
N
E
G
DC
L
K
VS
SQ
D3
D2
D1
D0
D2
D1
D0
A19
A18
A17
A16
A18
A17
A16
VDDPA2
VSSPA2
VDDPA1
VSSPA1
VSSPA2
VDDPA1
VSSPA1
XI
XO
VDDQ3
VSSQ
VDD1
VSS
A15
A14
A13
A12
A11
A10
A14
A13
A12
A11
A10
A9
A8
A7
A8
A7
VDD1
VSS
VDDQ3
VSSQ
A6
A5
A4
A3
A2
A1
A5
A4
A3
A2
A1
NMI
WR
RD
ROMOE
ROMWE
CS0
CS1
CS1
PORTA7
PORTA6
PORTA5
PORTA4
PORTA3
PORTA2
PORTA1
PORTA0
PORTA6
PORTA5
PORTA4
PORTA3
PORTA2
PORTA1
PORTA0
CONFIDENTIAL
86
LC-26GA5E
LC-32GA5E
LC-32GA5E
LC-37GA5E
3.2. Video Image Processor Block Diagram, IC2201
A/
D
Cl
a
m
p
D
R
R
G
B
(
23:
0)
D
G
R
G
B
(23:
0)
DV
S
, DHS
,
DE
N
, DCLK
NM
I
In
te
rr
upt
C
ont
ro
ll
e
r
Rx
D
Tx
D
UART
W
a
tc
hdog a
n
d
Ti
m
e
rs
P
ro
ces
so
r R
O
M
/
R
A
M
I
n
te
rf
ace
16
-B
it
M
ic
ropr
oc
e
s
s
o
r
P
o
rt
A & P
o
rt
D
(7
:0
)
GP
IO
PW
M
IR
D
e
c
ode
r
A
(19:
1)
D
(15:
0)
CS
(1
:0
)
2-
W
ir
e
Se
ri
a
l
M
icr
o
p
ro
cesso
r B
u
s
Mem
ory
Ou
t Bu
s
Me
m
o
ry
B
u
ffe
r
P
ro
c
e
sso
r
Me
m
o
ry
In
te
rf
ace
Mem
ory
In
Bu
s
OS
D
P
W
13
06
In
te
rn
al
B
lo
c
k D
iag
ra
m
ADC
Sy
n
c
P
ro
cessi
n
g
HS
HS
Y
N
C
,
V
SYN
C
SOY
S
tr
ippe
r
SOY
IN
FI
LT
PL
L
CL
K
R/
P
r
G/
Y
B/
P
b
A/
D
Cl
a
m
p
A/
D
Cl
a
m
p
VS
Po
w
e
rO
n
R
eset
R
ESET
R
eset
XI
XO
P
LL a
n
d
O
s
cil
lat
o
r
M
C
L
K
DCL
K
U
C
L
K
S
c
a
li
ng &
Vi
d
e
o
En
h
a
n
c
e
m
e
n
t
Co
lo
r
Ma
tr
ix
OS
D
an
d
Ga
in
Co
lo
r
Loo
k
u
p
Ta
b
le
s
Di
s
p
la
y
Ti
m
in
g
Ge
n
e
ra
to
r
Co
lo
r
S
p
ace
E
x
pa
nde
r
CS
C
Au
to
Im
a
g
e
CONFIDENTIAL
87
LC-26GA5E
LC-32GA5E
LC-32GA5E
LC-37GA5E
Table 2-2
provides detailed Display/Even Port pin descriptions.
Table 2-1 Signal Descriptions for the Analog Interface Pins
Name
Pin
Type
Function
RAIN
37
AI
Red/Green/Blue Analog Inputs. These pins receive the Red, Green and
Blue, or YPbPr/YCbCr/YUV analog signals from the analog video source.
For proper operation of the clamp feature, these inputs must be
AC-coupled.
Blue, or YPbPr/YCbCr/YUV analog signals from the analog video source.
For proper operation of the clamp feature, these inputs must be
AC-coupled.
GAIN
43
AI
BAIN
50
AI
SOGIN
44
AI
Analog Sync-On-Green or Sync-On-Luma input. Allows recovery of the
HSYNC signal when this pin is AC-coupling to the Green (Red or Blue)
analog signal source. If not used, this pin should be left unconnected.
HSYNC signal when this pin is AC-coupling to the Green (Red or Blue)
analog signal source. If not used, this pin should be left unconnected.
FILT
23
AI
External PLL Loop Filter. When using the on-chip PLL, this pin must be
connected to an external filter network.
connected to an external filter network.
HSYNC
65
DIS
Horizontal Synchronization Input. This digital input signal controls the
horizontal scan frequency by synchronizing the start of the horizontal
scan. The logic polarity of this signal is controlled by the HSPOL bit.
horizontal scan frequency by synchronizing the start of the horizontal
scan. The logic polarity of this signal is controlled by the HSPOL bit.
VSYNC
64
DIS
Vertical Synchronization Input. This digital signal controls the vertical scan
frequency.
frequency.
Table 2-2 Display/Even Port Pin Descriptions
Name
Pin(s)
Type
Function
DCLK
106
OSR
DPort Pixel Clock. Output clock for the display port pixel data. DCLK is
enabled by the DCLKEN bit and can be inverted by the DCPOL bit. DCLK
can be set to run at ½ pixel rate, for dual pixel output mode, by setting the
DCK2EN bit. The internal DCLK clock domain can be disabled by the
DCLKOFF bit to reduce power consumption.
enabled by the DCLKEN bit and can be inverted by the DCPOL bit. DCLK
can be set to run at ½ pixel rate, for dual pixel output mode, by setting the
DCK2EN bit. The internal DCLK clock domain can be disabled by the
DCLKOFF bit to reduce power consumption.
DCLKNEG
107
OSR
DPort Pixel Clock.
DVS
101
OS
DPort Vertical Sync. DVS can be either active-high or active-low depending
on the VSPOL bit. Width and timing is controlled by the VPLSE and VDLY
registers.
on the VSPOL bit. Width and timing is controlled by the VPLSE and VDLY
registers.
DHS
102
OS
DPort Vertical Sync. DHS can be either active-high or active-low depending
on the HSPOL bit. Sync width can be controlled by the HPLSE register.
on the HSPOL bit. Sync width can be controlled by the HPLSE register.
DEN
103
OS
DPort Pixel Enable. This signal is active whenever valid data is present.
The polarity is specified by the DENPOL bit.
The polarity is specified by the DENPOL bit.
3.3. Description of Pins IC2201
CONFIDENTIAL
88
LC-26GA5E
LC-32GA5E
LC-32GA5E
LC-37GA5E
3.3. Description of Pins IC2201, continued
DER0
98
OSR
DEPort Red Pixel Data. In dual pixel output mode these pins are the EVEN
red outputs.
red outputs.
DER1
97
OSR
DER2
94
OSR
DER3
93
OSR
DER4
92
OSR
DER5
91
OSR
DER6
90
OSR
DER7
89
OSR
DEG0
88
OSR
DEPort Green Pixel Data. In dual pixel output mode these pins are the
EVEN green outputs.
EVEN green outputs.
DEG1
87
OSR
DEG2
86
OSR
DEG3
85
OSR
DEG4
82
OSR
DEG5
81
OSR
DEG6
80
OSR
DEG7
79
OSR
DEB0
78
OSR
DEPort Blue Pixel Data. In dual pixel output mode these pins are the EVEN
blue outputs.
blue outputs.
DEB1
77
OSR
DEB2
74
OSR
DEB3
73
OSR
DEB4
71
OSR
DEB5
70
OSR
DEB6
67
OSR
DEB7
66
OSR
Table 2-2 Display/Even Port Pin Descriptions (continued)
Name
Pin(s)
Type
Function
CONFIDENTIAL
Click on the first or last page to see other LC-37GA5E (serv.man17) service manuals if exist.