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86

3

125

VREFAU

OBL

Reference Voltage, Audio

87

2

126

VSUP8.0AU

SUPPLY

OBL

Supply Voltage Analog Audio, 8.0 V

88

1

127

GND

SUPPLY

OBL

Ground Platform

71

P37 /
656IO7

IN/OUT

LV

Port 3, Bit 7 Input/Output
Digital 656 Bus 7 Input/Output

72

P36 /
656IO6

IN/OUT

LV

Port 3, Bit 6 Input/Output
Digital 656 Bus 6 Input/Output

73

P35 /
656IO5

IN/OUT

LV

Port 3, Bit 5 Input/Output
Digital 656 Bus 5 Input/Output

74

P34 /
656IO4

IN/OUT

LV

Port 3, Bit 4 Input/Output
Digital 656 Bus 4 Input/Output

75

P33 /
656IO3

IN/OUT

LV

Port 3, Bit 3 Input/Output
Digital 656 Bus 3 Input/Output

76

GNDEIO

SUPPLY

OBL

Ground Extended I/O Ports

77

VSUP3.3EIO

SUPPLY

OBL

Supply Voltage Extended I/O Ports, 3.3 V

78

P32 /
656IO2

IN/OUT

LV

Port 3, Bit 2 Input/Output
Digital 656 Bus 2 Input/Output

79

P31 /
656IO1

IN/OUT

LV

Port 3, Bit 1 Input/Output
Digital 656 Bus 1 Input/Output

80

P30 /
656IO0

IN/OUT

LV

Port 3, Bit 0 Input/Output
Digital 656 Bus 0 Input/Output

81

P26 /
656VIO

IN/OUT

LV

Port 2, Bit 6 Input/Output
Digital 656 Vsync Input/Output

82

P25 /
656HIO

IN/OUT

LV

Port 2, Bit 5 Input/Output
Digital 656 Hsync Input/Output

83

P24 /
656CLKIO

IN/OUT

LV

Port 2, Bit 4 Input/Output
Digital 656 Clock Input/Output

31

ADB19

OUT

LV

Address Bus 19 Output

21

ADB18

OUT

LV

Address Bus 18 Output

19

ADB17

OUT

LV

Address Bus 17 Output

22

ADB16

OUT

LV

Address Bus 16 Output

23

ADB15

OUT

LV

Address Bus 15 Output

18

ADB14

OUT

LV

Address Bus 14 Output

17

ADB13

OUT

LV

Address Bus 13 Output

26

ADB12

OUT

LV

Address Bus 12 Output

14

ADB11

OUT

LV

Address Bus 11 Output

96

ADB10

OUT

LV

Address Bus 10 Output

15

ADB9

OUT

LV

Address Bus 9 Output

16

ADB8

OUT

LV

Address Bus 8 Output

27

ADB7

OUT

LV

Address Bus 7 Output

28

ADB6

OUT

LV

Address Bus 6 Output

29

ADB5

OUT

LV

Address Bus 5 Output

30

ADB4

OUT

LV

Address Bus 4 Output

84

ADB3

OUT

LV

Address Bus 3 Output

85

ADB2

OUT

LV

Address Bus 2 Output

86

ADB1

OUT

LV

Address Bus 1 Output

87

ADB0

OUT

LV

Address Bus 0 Output

88

DB0

IN/OUT

LV

Data Bus 0 Input/Output

89

DB1

IN/OUT

LV

Data Bus 1 Input/Output

90

DB2

IN/OUT

LV

Data Bus 2 Input/Output

91

DB3

IN/OUT

LV

Data Bus 3 Input/Output

92

DB4

IN/OUT

LV

Data Bus 4 Input/Output

93

DB5

IN/OUT

LV

Data Bus 5 Input/Output

94

DB6

IN/OUT

LV

Data Bus 6 Input/Output

95

DB7

IN/OUT

LV

Data Bus 7 Input/Output

32

RDQ

OUT

LV

Data Read Enable Output

33

WRQ

OUT

LV

Data Write Enable Output

34

OCF

OUT

LV

Opcode Fetch Output

35

ALE

OUT

LV

Address Latch Enable Output

36

RSTQ

OUT

LV

Internal CPU Reset Output

97

PSENQ

OUT

LV

Program Store Enable Output

20

PSWEQ

OUT

LV

Program Store Write Enable Output

51

XROMQ

IN

OBL

External ROM Enable Input

52

EXTIFQ

IN

LV

Enable External Interface Input

24

STOPQ

IN

LV

Stop CPU Input

25

ENEQ

IN

LV

Enable Emulation Input

 

Pin 

Function 

Description 

2, 3 

DCAP2, DCAP1 

Charge pump switching pins.  DCAP1 (pin 3) is a free running 300kHz square 
wave between VDDA and DGND (12Vpp nominal).  DCAP2 (pin 2) is level shifted 
10 volts above DCAP1 (pin 3) with the same amplitude (12Vpp nominal), 
frequency, and phase as DCAP1. 

4, 9 

V5D, V5A 

Digital 5VDC, Analog 5VDC 

5, 8,  

17 

AGND1, AGND2, 

AGND3 

Analog Ground 

6 

REF 

Internal reference voltage; approximately 1.0 VDC. 

7 

OVERLOADB 

A logic low output indicates the input signal has overloaded the amplifier. 

10, 14 

OAOUT1, OAOUT2 

Input stage output pins. 

11, 15 

INV1, INV2 

Single-ended inputs.  Inputs are a “virtual” ground of an inverting opamp with 
approximately 2.4VDC bias. 

12 

MUTE 

When set to logic high, both amplifiers are muted and in idle mode.  When low 
(grounded), both amplifiers are fully operational.  If left floating, the device stays in 
the mute mode.  This pin should be tied to GND if not used. 

16 

BIASCAP 

Input stage bias voltage (approximately 2.4VDC). 

18 

SLEEP 

When set to logic high, device goes into low power mode.  If not used, this pin 
should be grounded 

19 

FAULT 

A logic high output indicates thermal overload, or an output is shorted to ground, 
or another output. 

20, 35 

PGND2, PGND1 

Power Grounds (high current) 

22 

DGND 

Digital Ground.  Connect to AGND locally (near the TA2024). 

24, 27; 

31, 28 

OUTP2 & OUTM2; 

OUTP1 & OUTM1 

Bridged output pairs 

25, 26, 

29, 30 

VDD2, VDD2 
VDD1, VDD1 

Supply pins for high current H-bridges, nominally 12VDC. 

13, 21, 
23, 32, 

34 

NC 

Not connected.  Not bonded internally. 

33 VDDA 

Analog 

12VDC 

36 

CPUMP 

Charge pump output (nominally 10V above VDDA) 

1 

5VGEN 

Regulated 5VDC source used to supply power to the input section (pins 4 and 9). 

 

FAULT

PGND2

NC

NC

VDD2

OUTM2

OUTM1

VDD1

NC

VDDA

NC

PGND1

CPUMP

DCAP2

AGND3

BIASCAP

INV2

OAOUT2

MUTE

INV1

OAOUT1

V5A

AGND2

OVERLOADB

REF

AGND1

V5D

DCAP1

30

19

20

21

22

23

24

25

26

27

28

29

1

15

14

13

11

10

12

9

8

7

6

5

4

3

2

16

17

18

+5VGEN

36

31

32

33

34

35

OUTP1

VDD1

VDD2

OUTP2

DGND

NC

SLEEP

 

 

O

O

VD D A

+5VG EN

D C AP2

D C AP1

C PU M P

10

11

20

1

33

29

26

7

19

31

28

24

27

36

2

3

15

14

12

16

18

SLEEP

5V

5V

R EF

6

VDD1

PG ND1

VDD1

PG ND1

VDD2

VDD2

PG ND2

PG ND2

4

5

V5D

8

AGN D 1

AGN D 2

V5A

22

D GN D

VD D 1

PGN D 2

35

PGN D 1

VD D 2

Processing

&

M odulation

Processing

&

M odulation

9

AGN D 3

17

13

NC

21

23

25

30

32

34

VD D 1

VD D 2