DOWNLOAD Sharp LC-32CT2E (serv.man2) Service Manual ↓ Size: 4.79 MB | Pages: 109 in PDF or view online for FREE

Model
LC-32CT2E (serv.man2)
Pages
109
Size
4.79 MB
Type
PDF
Document
Service Manual
Brand
Device
TV / LCD
File
lc-32ct2e-sm2.pdf
Date
PREV: Sharp LC-32CT2E Handy Guide

Sharp LC-32CT2E (serv.man2) Service Manual ▷ View online

1
TP158
5V_STBY
12V_VCC
3V3_STBY
3V3SDDAC
TP157
1
TP143
1
3.3V_HDMI
3V3HDDAC
1V8_VDD_HDMI
3V3USB
3V3_LPW
24V_VCC
5V_VCC
3V3_VCC
3V3IO
1V8DDR2
3V3DMD
3V3_CI
C125
16V
100n
16V
100n
C126
F3
600R
100n
16V
C217
6V3
220u
C56
50V
1n
C331
C114
100n
16V
16V
100n
C124
1.8V
16V
100n
C101
C102
100n
16V
16V
100n
C99
C100
100n
16V
100n
16V
C97
1V8DDR2
100n
16V
C98
C95
16V
100n
600R
F2
C96
16V
100n
C57
220u
6V3
C328
1n
50V
16V
100n
C93
C94
100n
16V
1V05CORE
1V05
16V
100n
C216
C215
100n
16V
C322
10u
6V3
50V
1n
C336
100n
16V
C91
3V3_VCC
3V3HDDAC
3V3SDDAC
C214
100n
16V
16V
100n
C209
6V3
10u
C326
C335
1n
50V
C92
16V
100n
3V3_VCC
F5
600R
50V
1n
C337
6V3
220u
C60
100n
16V
C89
1V05
C206
100n
16V
100n
16V
C90
1V05
600R
F10
16V
100n
C207
1V05DDR2
C205
100n
16V
C325
10u
6V3
1V05DPLL
6V3
10u
C319
C87
16V
100n
1V05
600R
F4
1V05SPLL
C192
16V
100n
100n
16V
C179
F9
600R
C88
100n
16V
100n
16V
C85
16V
100n
C86
C83
100n
16V
F1
600R
C84
16V
100n
C55
220u
6V3
C329
1n
50V
16V
100n
C81
C82
100n
16V
TP196
1
F7
600R
C79
100n
16V
16V
100n
C80
C77
100n
16V
16V
100n
C78
100n
16V
C75
16V
100n
C76
C73
100n
16V
C74
16V
100n
C71
16V
100n
3V3_VCC
16V
100n
C188
C318
6V3
10u
50V
C333
1n
16V
100n
C72
3V3_VCC
3V3IO
3V3USB
600R
F6
1V05SPLL
1V05DPLL
1V05CORE
1V8DDR2
3V3IO
uPD61305F1
U1
R15
R13
R11
P14
P12
P10
N15
N13
N11
M16
M14
M12
M10
L17
L15
U15
L11
K16
K14
K12
AC13
Y19
U20
R20
N20
G19
G14
F14
E14
H7
H6
T12
T14
U11
U13
L13
J7
G5
F5
D5
W7
C22
B25
J20
P21
AA14
AC20
Y20
Y17
Y15
Y13
Y11
Y9
AC8
Y7
T21
G20
G18
G23
F15
E15
W26
W25
V24
G11
G9
G8
B2
G7
G6
T17
P17
U17
R17
N17
F7
F6
T16
P16
U16
R16
N16
A10
A26
Y8
Y10
Y12
Y14
Y16
Y18
Y24
AA5
AA24
AB5
AC12
AC5
AB26
AB25
AB14
AC14
AC18
AD5
AD8
AD14
W20
V26
V25
V20
U24
U23
U22
U14
U12
T22
T20
AF19
T13
T11
R24
R14
R12
R10
P15
P13
P11
N26
N25
N14
N12
N10
M20
M17
M15
M13
M11
L20
L16
L14
L12
K24
K20
K17
K15
K13
K11
H20
H5
G24
E5
C5
B22
B5
B4
B3
B1
T15
AF5
AE16
AE5
GND_30
GND_31
GND_32
GND_33
GND_34
GND_35
GND_36
GND_37
GND_38
GND_39
GND_40
GND_41
GND_42
GND_43
GND_44
GND_45
GND_46
GND_47
GND_48
GND_49
GND_50
GND_51
GND_52
GND_53
GND_54
GND_55
GND_56
GND_57
GND_58
GND_59
GND_60
GND_61
GND_62
GND_63
GND_64
GND_65
GND_66
GND_67
GND_68
GND_69
GND_70
GND_71
GND_72
GND_73
GND_74
GND_75
GND_76
GND_77
GND_78
GND_79
GND_80
GND_81
GND_82
GND_83
GND_84
GND_85
GND_86
GND_87
GND_88
GND_89
GND_90
GND_91
GND_92
GND_93
GND_94
GND_95
GND_96
GND_97
GND_98
GND_99
GND_100
GND_101
GND_102
GND_103
GND_104
GND_105
GND_106
PLAUGND
PLHDGND
PLSOGND
PLSVGND
PLSYGND
PLUMGND
PLURGND
PLAUVDD
PLHDVDD
PLSOVDD
PLSVVDD
PLSYVDD
PLUMVDD
PLURVDD
VDD3_1
VDD3_2
VDD3_3
VDD3_4
VDD3_5
VDD3_6
VDD3_7
VDD3_8
VDD3_9
VDD3_10
VDD3_11
VDD3_12
VDD3_13
VDD3_14
VDD3_15
VDD3_16
VDD3_17
VDD3_18
VDD3_19
VDD3_20
VDD3_21
VDD3_22
VDD3_23
VDD3_24
VDD3_25
VDD3_26
VDD3_27
VDD3_28
VDD3_29
VDD3_30
VDD3_31
VDD3_32
CVDD_1
CVDD_2
CVDD_3
CVDD_4
CVDD_5
CVDD_6
CVDD_7
CVDD_8
CVDD_9
CVDD_10
CVDD_11
CVDD_12
CVDD_13
CVDD_14
CVDD_15
CVDD_16
CVDD_17
CVDD_18
CVDD_19
CVDD_20
CVDD_21
CVDD_22
CVDD_23
CVDD_24
CVDD_25
CVDD_26
CVDD_27
CVDD_28
CVDD_29
CVDD_30
CVDD_31
CVDD_32
CVDD_33
CVDD_34
CVDD_35
CVDD_36
5
100n
C69
16V
1V8DDR2
10k
R457
R452
10k
16V
100n
C220
6V3
10u
C316
C317
10u
6V3
1V05DDR2
1V8DDR2
R484
150R
150R
R498
1V8DDR2
uPD61305F1
U1
T7
N7
N6
N5
R1
L7
AE2
T5
W2
T6
V6
C1
K2
V7
Y6
AA2
P1
H2
J6
AC2
L6
D2
AF1
F2
T10
L10
U10
K10
M4
M3
AF2
M7
U6
M6
U5
AE1
N1
K1
M5
AD3
AB3
D1
T1
AC1
F1
C2
P7
Y3
K7
R7
G3
J3
W1
AA1
H1
U7
K6
W6
E3
N4
T4
R2
R6
AD1
Y1
E1
J1
AD2
Y2
E2
J2
C4
F3
L5
H3
K3
L4
AC4
AC3
L3
AF4
AB4
AA4
AF3
AE4
AD4
Y4
V5
AA3
W3
K5
V4
Y5
V3
W4
H4
C3
F4
D4
G4
E4
J4
J5
AE3
W5
D3
K4
U3
R5
U4
N3
AB2
G2
AB1
G1
T2
P6
P5
L1
U1
L2
U2
M1
V2
P4
P3
M2
R4
N2
V1
P2
R3
T3
A0
A1
A10
A11
A12
A14
A15
A2
A3
A4
A5
A6
A7
A8
A9
BA0
BA1
CASB
CK0
CK1
CKB0
CKB1
CKE
CKERSTB
CSB0
CSB1
DM0
DM1
DM2
DM3
DQ0
DQ1
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ2
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ3
DQ30
DQ31
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQS0
DQS1
DQS2
DQS3
DQSB0
DQSB1
DQSB2
DQSB3
ODT0
ODT1
RASB
WEB
GND_1
GND_2
GND_3
GND_4
GND_5
GND_6
GND_7
GND_8
GND_9
GND_10
GND_11
GND_12
GND_13
GND_14
GND_15
GND_16
GND_17
GND_18
GND_19
GND_20
GND_21
GND_22
GND_23
GND_24
GND_25
GND_26
GND_27
GND_28
GND_29
RQ0
RQ1
VDD10_1
VDD10_2
VDD10_3
VDD10_4
VDD18_1
VDD18_2
VDD18_3
VDD18_4
VDD18_5
VDD18_6
VDD18_7
VDD18_8
VDD18_9
VDD18_10
VDD18_11
VDD18_12
VDD18_13
VDD18_14
VDD18_15
VDD18_16
VDD18_17
VDD18_18
VDD18_19
VDD18_20
VDD18_21
VDD18_22
VREF0
VREF1
2
TP236
1
TP197
1
5V_CI
NEC DDR & POWER
ERTUG BAL
11 NEC DDR & SUPPLY
19
17mb38
-1
8
7
6
5
4
3
2
1
A
B
C
D
E
F
A X M
1
2
3
4
5
6
7
8
A
B
C
D
E
F
OF:
A3
PROJECT NAME :
VESTEL
SCH NAME :
DRAWN BY :
SHEET:
04-12-2009_16:33
TP199
1
1V26_STBY
TP240
AVDD_33
TP239
VDDP
1V05_HDMI
TP243
TP259
1V05CORE
TP260
1V05DDR2
TP269
1V05SPLL
1V05DPLL
TP270
TP242
VDDC
TP142
1
TP241
1
TP201
1
TP202
1
TP198
1
TP271
1
1V8_HDMI
TP272
1
TP144
1
2V6_VCC
TP249
1
TP273
1
TP228
1
VDDM
VDD_DMC
VDD_DMQ
TP276
1
TP275
1
TP225
1
TP267
1
TP232
1
TP231
1
TP230
1
TP274
1
5V_SPDIF
TP233
1
5V_AV
5V_TUN
8V_VCC
DQS1
DQS0
BA1
BA0
ODT0
WEB
RASB
A0
CKB0
DQ14
DQ8
DQ7
DQ6
DQ5
DQ2
DQ1
DQ0
DQSB1
DQSB0
DQ15
DQ12
DQ9
DQ10
DQ13
DQ11
DQ3
DQ4
DM1
DM0
CSB1
CSB0
CKE
CK0
CASB
A9
A8
A7
A6
A5
A4
A3
A2
A12
A11
A10
A1
DQSB3
A15
A14
DQSB2
DQS3
DQS2
DQ27
DQ28
DQ31
DQ25
DQ30
DQ29
DQ26
DQ24
DQ18
DQ22
DQ23
DQ19
DQ20
DQ21
DQ17
DQ16
DM3
DM2
CKB1
CK1
VREFEMMA
VREFEMMA
%1
%1
%1
%1
3V3_STBY
1V26_STBY
1V05
5V
5V_STBY
12V
24V
1V8
3V3
2V6
8V
C298
6V3
1u
R41
22R
C289
100n
16V
22R
R40
1u
6V3
C296
16V
100n
C285
U3
G8
G2
H7
H3
H1
H9
F1
F7
E8
F3
F9
C8
C2
D7
D3
D1
D9
B1
B9
B7
A8
B3
A2
E2
L1
R3
R7
R8
M8
M3
M7
N2
N8
N3
N7
P2
P8
P3
M2
P7
R2
L2
L3
K7
L7
K3
L8
K2
J8
K8
K9
A3
E3
J3
N1
P9
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
J7
J2
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
A1
E1
J9
M9
R1
J1
VDDL
VDD5
VDD4
VDD3
VDD2
VDD1
VDDQ10
VDDQ9
VDDQ8
VDDQ7
VDDQ6
VDDQ5
VDDQ4
VDDQ3
VDDQ2
VDDQ1
VREF
VSSDL
VSSQ10
VSSQ9
VSSQ8
VSSQ7
VSSQ6
VSSQ5
VSSQ4
VSSQ3
VSSQ2
VSSQ1
VSS5
VSS4
VSS3
VSS2
VSS1
ODT
CK_P
CK
CKE
CS_P
WE_P
CAS_P
RAS_P
BA1
BA0
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
NC6
NC5
NC4
NC3
NC2
NC1
UDM
UDQS_P
UDQS
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
LDM
LQDS_P
LQDS
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
R314
22R
22R
R311
R307
22R
22R
R305
22R
R318
R317
22R
22R
R309
R312
22R
22R
R315
R319
22R
22R
R328
R327
22R
22R
R303
R304
22R
22R
R329
R320
22R
22R
R316
R313
22R
22R
R310
R306
22R
22R
R308
R335
22R
150R
R500
22R
R334
C286
100n
16V
1V8DDR2
10k
R459
10k
R454
16V
100n
C222
16V
100n
C287
16V
100n
C127
C288
100n
16V
16V
100n
C281
C282
100n
16V
16V
100n
C283
C284
100n
16V
16V
100n
C277
C278
100n
16V
6V3
220u
C58
1V8DDR2
16V
100n
C279
17mb38
-1
ERTUG BAL
NEC DDR2 (1)
19
12 NEC DDR (1)
04-12-2009_16:33
8
7
6
5
4
3
2
1
A
B
C
D
E
F
A X M
1
2
3
4
5
6
7
8
A
B
C
D
E
F
OF:
A3
PROJECT NAME :
VESTEL
SCH NAME :
DRAWN BY :
SHEET:
DQS1
DQS0
BA1
BA0
ODT_L
ODT_L
ODT0
CKE_
CKE_
WEB_
WEB_
WEB
CASB_
CASB_
RASB_
RASB_
RASB
BA_2H
BA_2L
BA_2L
CSB_0
CSB_0
BA_0
BA_0
BA_1
BA_1
A_0
A_0
A_1
A_1
A_2
A_2
A_3
A_3
A_4
A_4
A_5
A_5
A_6
A_6
A_7
A_7
A_8
A_8
A_9
A_9
A_10
A_10
A_11
A_11
A_12
A_12
A0
CKB0
DQ14
DQ8 DQ7
DQ6 DQ5
DQ2 DQ1 DQ0
VREFDDR2_1
VREFDDR2_1
DQSB1
DQSB0
DQ15
DQ12
DQ9
DQ10
DQ13
DQ11
DQ3
DQ4
DM1
DM0
CSB1
CSB0
CKE
CK0
CASB
A9
A8
A7
A6
A5
A4
A3
A2
A12
A11
A10
A1
%1
%1
%1
EDE5116AJBG-6E-E
NEC DDR2 (2)
ERTUG BAL
13 NEC DDR (2)
17mb38
-1
19
8
7
6
5
4
3
2
1
A
B
C
D
E
F
A X M
1
2
3
4
5
6
7
8
A
B
C
D
E
F
OF:
A3
PROJECT NAME :
VESTEL
SCH NAME :
DRAWN BY :
SHEET:
04-12-2009_16:33
6V3
220u
C59
1u
C297
6V3
100n
C280
16V
C273
100n
16V
6V3
C295
1u
R43
22R
22R
R42
U4
G8
G2
H7
H3
H1
H9
F1
F7
E8
F3
F9
C8
C2
D7
D3
D1
D9
B1
B9
B7
A8
B3
A2
E2
L1
R3
R7
R8
M8
M3
M7
N2
N8
N3
N7
P2
P8
P3
M2
P7
R2
L2
L3
K7
L7
K3
L8
K2
J8
K8
K9
A3
E3
J3
N1
P9
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
J7
J2
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
A1
E1
J9
M9
R1
J1
VDDL
VDD5
VDD4
VDD3
VDD2
VDD1
VDDQ10
VDDQ9
VDDQ8
VDDQ7
VDDQ6
VDDQ5
VDDQ4
VDDQ3
VDDQ2
VDDQ1
VREF
VSSDL
VSSQ10
VSSQ9
VSSQ8
VSSQ7
VSSQ6
VSSQ5
VSSQ4
VSSQ3
VSSQ2
VSSQ1
VSS5
VSS4
VSS3
VSS2
VSS1
ODT
CK_P
CK
CKE
CS_P
WE_P
CAS_P
RAS_P
BA1
BA0
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
NC6
NC5
NC4
NC3
NC2
NC1
UDM
UDQS_P
UDQS
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
LDM
LQDS_P
LQDS
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
C274
16V
100n
1V8DDR2
100n
16V
C275
100n
C276
16V
C269
16V
100n
16V
100n
C270
100n
C271
16V
100n
16V
C272
C263
16V
100n
C129
16V
100n
16V
C266
100n
1V8DDR2
10k
R458
10k
R453
C221
100n
16V
C267
16V
100n
22R
R333
R481
150R
R332
22R
ODT_L
CKE_
WEB_
CASB_
RASB_
BA_2H
CSB_0
BA_0
BA_1
A_0
A_1
A_2
A_3
A_6
A_7
A_8
A_9
A_10
A_11
A_12
VREFDDR2_2
VREFDDR2_2
DQSB3
A_15
A_15
A_14
A_14
A15
A14
DQSB2
DQS3
DQS2
DQ27
DQ28
DQ31
DQ25
DQ30
DQ29
DQ26
DQ24
DQ18
DQ22
DQ23
DQ19
DQ20
DQ21
DQ17
DQ16
DM3
DM2
CKB1
CK1
%1
%1
%1
EDE5116AJBG-6E-E
3V3IO
R66
10k
3V3IO
3V3IO
10k
R36
TP1
S2
C252
100n
16V
3V3IO
10k
R14
R6
10k
10k
R7
R10
10k
10k
R11
R1
10k
10k
R2
10k
R12
R13
10k
R3
10k
R39
10k
10k
R48
10k
R37
R38
10k
R45
10k
3V3IO
10k
R47
10k
R46
R8
10k
10k
R9
R4
10k
10k
R5
R21
10k
R22
10k
10k
R25
R26
10k
10k
R17
R18
10k
R15
10k
R16
10k
10k
R19
R20
10k
10k
R23
R24
10k
3V3IO
R27
10k
74V1G08
U21
5
4
3
2
1 A
B
GND
Y
VCC
10k
R28
10k
R49
16V
100n
C254
C247
100n
16V
C248
16V
100n
3V3IO
3V3IO
10k
R44
S29GL064NFFI
U2
E2
D2
C2
A2
B2
D3
C3
A3
B6
A6
C6
D6
B7
A7
C7
D7
E7
B3
C4
D5
D4
C5
B8
C8
F8
F2
G2
B5
A5
D8
F1
E3
H3
E4
H4
H5
E5
H6
E6
F3
G3
F4
G4
F5
G6
F6
G7
A1
A8
B1
C1
D1
E1
G1
G8
H1
H8
A4
F7
B4
G5
E8
H2
H7
VSS3
VSS2
VSS1
VCC
WP#/ACC
BYTE#
RY/BY#
NC_10
NC_9
NC_8
NC_7
NC_6
NC_5
NC_4
NC_3
NC_2
NC_1
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
VIO2
VIO1
WE#
RESET#
OE#
CE#
A24
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
uPD61305F1
U1
AA16
AC15
AB16
V21
AC16
V23
U21
AD26
W23
AB20
AA20
AA19
V22
Y22
AC25
W22
Y23
AF26
AC26
Y21
W21
AB24
AD25
AB13
AA13
W24
AE26
AF17
AE17
AD17
AC17
AB17
AA17
AF18
AE18
AD18
AB18
AA18
AE19
AD19
AC19
AB19
AD20
AF20
AE20
AF21
AE21
AD21
AC21
AB21
AA21
AF22
AE22
AD22
AC22
AB22
AA22
AF23
AE23
AD23
AC23
AB23
AA23
AF24
AE24
AD24
AC24
AF25
AE25
RADD0
RADD1
RADD2
RADD3
RADD4
RADD5
RADD6
RADD7
RADD8
RADD9
RADD10
RADD11
RADD12
RADD13
RADD14
RADD15
RADD16
RADD17
RADD18
RADD19
RADD20
RADD21
RADD22
RADD23
RADD24
RADD25
RDATA0
RDATA1
RDATA2
RDATA3
RDATA4
RDATA5
RDATA6
RDATA7
RDATA8
RDATA9
RDATA10
RDATA11
RDATA12
RDATA13
RDATA14
RDATA15
FCSB0
FCSB1
FCSB2
FCSB3
FOEB
FWEB
GCSB0
GCSB1
GPIO_CD1B
GPIO_CD2B
GPIO_IREQB
GPIO_RESET
GPIO_VS1B
GRDYB
IOIS16
IORDB
IOWRB
NALE
NCLE
NR/BB
PCE0B
PCE1B
REGB
SMVCC1
STP0CLK
STP0EN
STP0STRT
4
3V3IO
NEC FLASH
ERTUG BAL
MB38-1
19
14 NEC FLASH
8
7
6
5
4
3
2
1
A
B
C
D
E
F
A X M
1
2
3
4
5
6
7
8
A
B
C
D
E
F
OF:
A3
PROJECT NAME :
VESTEL
SCH NAME :
DRAWN BY :
SHEET:
04-12-2009_16:33
nCI_IRQ
FWEB_FLASH
FWEB_FLASH
nRESET
RADD19
RADD19
RADD19
RADD18
RADD18
RADD18
RADD17
RADD17
RADD17
RADD16
RADD16
RADD16
RADD15
RADD15
RADD15
RADD14
RADD14
RADD14
RADD13
RADD13
RADD13
RADD12
RADD12
RADD12
RADD11
RADD11
RADD11
RADD10
RADD10
RADD10
RADD9
RADD9
RADD9
RDATA15
RDATA15
RDATA14
RDATA14
RDATA13
RDATA13
RDATA12
RDATA12
RDATA11
RDATA11
RDATA10
RDATA10
RDATA9
RDATA9
RADD7
RADD7
RADD7
RADD8
RADD8
RADD8
RADD6
RADD6
RADD6
RADD5
RADD5
RADD5
RADD4
RADD4
RADD4
RADD3
RADD3
RADD3
RADD2
RADD2
RADD2
RADD1
RADD1
RADD1
RADD0
RADD0
FCSB0
FCSB0
FWEB
FWEB
FOEB
FOEB
RDATA8
RDATA8
RDATA7
RDATA7
RDATA6
RDATA6
RDATA5
RDATA5
RDATA4
RDATA4
RDATA3
RDATA3
RDATA2
RDATA2
RDATA1
RDATA1
RDATA0
RDATA0
RADD25
RADD25
RADD24
RADD24
RADD23
RADD23
RADD22
RADD22
RADD21
RADD21
RADD20
RADD20
nCI_PWR
nCI_REG
nCS2
nCI_IOWR
nCI_VS
nCI_CD1
nCI_CD2
nCI_RESET
nRDY
nCI_IORD
NC
NC
FAST FLASH PROGRAMMING OPTION
RADD19 EJTAG Daisy Chain Setting 0=Reserved 1=Only Main CPU
RADD18 EJTAG DINT Enable Setting 0=Disable 1=Enable
RADD17 EJTAG or JTAG Setting 0=JTAG 1=EJTAG
RADD16 Test Please set 0.
RADD15 Test Please set 0.
RADD14 Test Please set 0.
RADD13 NAND Flash ROM CS pin selection 0=CS0 1=CS1
other: Prohibit
(if normal NAND Flash ROM is 512 Mb or less)
01: Address latch cycle: 4 times, command latch cycle: once
(if normal NAND Flash ROM is 256 Mb or less)
00: Address latch cycle: 3 times, command latch cycle: once
program is stored in the NAND boot mode (BOOT_MODE = 001 or 011)
Specifies the access method of NAND Flash ROM where the boot
Boot NAND ROM selection
RADD12 BOOT_NAND_SEL[1]
RADD11 BOOT_NAND_SEL[0]
other: Prohibit
011: Boot from the NAND Flash ROM or Memory Stick
001: Boot from the NAND Flash ROM
000: Normal (Not Mini Boot)
Boot mode setting: BOOT_MODE[2:0] =
RADD10 BOOT_MODE[2]
RADD9 BOOT_MODE[1]
RADD8 BOOT_MODE[0]
RADD7 ROM bus width setting 0=16-bit 1=8-bit
RADD6 ROM endian Setting 0=Little 1=Big
1:262.144 MHz
0: 327.680 MHz
MCLK_SEL=
RADD5 MCLK_SEL Unified memory clock frequency selection
11: Reserved (setting prohibited)
10: 218.450 MHz
01: 262.144 MHz
00: 327.680 MHz
CPUCLK_SEL[1:0]=
Main CPU clock frequency selection
RADD4 CPUCLK_SEL[1]
RADD3 CPUCLK_SEL[0]
RADD2 Test Please set 0.
RADD1 Test Please set 0.
RADD0 CPU endian Setting 0=Little 1=Big
Signal Description
STRAP OPTIONS
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
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