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This switch is used to open and close panel supply of TCON. It is controlled by port of main μController. 
Also with this circuit panel sequence could be adjusted correctly. 3 panel supplies are connected to this 

circuit. All of them are optional according to panels.

12.1

12.2

MX25L1005 is a CMOS 1,048,576 bit serial Flash memory, which is configured as 131,072 x 8 internally. 

The MX25L1005 feature a serial peripheral interface and software protocol allowing operation on a simple 
3-wire bus. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output 

(SO). SPI access to the device is enabled by CS# input. The MX25L1005 provide sequential read operation 

on whole chip. After program/erase command is issued, auto program/ erase algorithms which program/ 
erase and verify the specified page or sector/block locations will be executed. Program command is 

executed on page (256 bytes) basis, and erase command is executes on chip or sector(4K-bytes) or 
block(64K-bytes). To provide user with ease of interface, a status register is included to indicate the status 

of the chip. The status read command can be issued to detect completion status of a program or erase 

operation via WIP bit. When the device is not in operation and CS# is high, it is put in standby mode and 

draws less than 10uA DC current. The MX25L1005 utilize MXIC's proprietary memory cell, which reliably 

stores memory contents even after 100,000 program and erase cycles.



Serial Peripheral Interface (SPI) compatible -- Mode 0 and Mode 3



1,048,576 x 1 bit structure



32 Equal Sectors with 4K byte each, Any Sector can be erased individually



2 Equal Blocks with 64K byte each, Any Block can be erased individually



Single Power Supply Operation



2.7 to 3.6 volt for read, erase, and program operations



Latch-up protected to 100mA from -1V to Vcc +1V



Low Vcc write inhibit is from 1.5V to 2.5V

RATING

VALUE

Ambient Operating Temperature

0°C to 70°C

Storage Temperature

-55°C to 125°C

Applied Input Voltage

-0.5v to 4.6v

Applied Output Voltage

-0.5v to 4.6v

VCC to Ground Potential

-0.5v to 4.6v

8-PIN SOP (150mil)

SYMBOL

DESCRIPTION

CS#

Chip select

SI

Serial Data Input

SO

Serial Data Output

SCLK

Clock Input

HOLD#

Hold, to pause the device without 
deselecting the device

VCC

+3.3v Power Supply

GND

Ground

8-PIN SOP (150mil)

SYMBOL

DESCRIPTION

CS#

Chip select

SI

Serial Data Input

SO

Serial Data Output

SCLK

Clock Input

HOLD#

Hold, to pause the device without 
deselecting the device

VCC

+3.3v Power Supply

GND

Ground

13.4

13.2

13.3

13.1

The NAND flash 528-byte/ 264-word page is a family of non-volatile flash memories that uses the single 
level cell (SLC) NAND technology. It is referred to as the small page family.

The NAND512R3A2C, NAND512R4A2C, and NAND512W3A2C have a density of 512 Mbits and operate with 
either a 1.8 V or 3 V voltage supply. The size of a page is either 528 bytes (512 + 16 spare) or 264 words 
(256 + 8 spare) depending on whether the device has a x8 or x16 bus width.

The address lines are multiplexed with the Data Input/output signals on a multiplexed x8 or x16 
input/output bus. This interface reduces the pin count and makes it possible to migrate to other densities 
without changing the footprint.

To extend the lifetime of NAND flash devices it is strongly recommended to implement an error 
correction code (ECC). The use of ECC correction allows to achieve up to 100,000 program/erase cycles 
for each block. A write protect pin is available to give a hardware protection against program and erase 
operations.



High density NAND flash memories



512-Mbit memory array



Cost effective solutions for mass storage applications



NAND interface



x8 or x16 bus width



Multiplexed address/ data



Supply voltage: 1.8 V, 3 V



Page size



x8 device: (512 + 16 spare) bytes



x16 device: (256 + 8 spare) words



Block size



x8 device: (16K + 512 spare) bytes



x16 device: (8K + 256 spare) words



Page read/program



Random access: 12 μs (3 V)/15 μs (1.8 V) (max)



Sequential access: 30 ns (3 V)/50 ns (1.8 V) (min)



Page program time: 200 μs (typ)



Copy back program mode



Fast block erase: 2 ms (typ)



Status register

14.2

14.1