Sharp LC-22LE240K Service Manual ▷ View online
37
LC-22LE240
8. DDR2 SDRAM K4T1G164QF (U155)
Description:
The 1Gb DDR2 SDRAM is organized as a 16Mbit x 8 I/Os x 8 banks, 8Mbit x 16 I/Os x 8
The 1Gb DDR2 SDRAM is organized as a 16Mbit x 8 I/Os x 8 banks, 8Mbit x 16 I/Os x 8
banks device. This synchronous device achieves high speed double-data-rate transfer
rates of up to 1066Mb/sec/pin (DDR2-1066) for general applications. The chip is designed
to comply with the following key DDR2 SDRAM fea-tures such as posted CAS with
additive latency, write latency = read latency - 1, Off-Chip Driver(OCD) impedance
adjustment and On Die Termination. All of the control and address inputs are
synchronized with a pair of exter-nally supplied differential clocks. Inputs are latched at
the crosspoint of dif-ferential clocks (CK rising and CK falling). All I/Os are synchronized
with a pair of bidirectional strobes (DQS and DQS) in a source synchronous fash-ion. The
address bus is used to convey row, column, and bank address information in a RAS/CAS
multiplexing style. For example, 1Gb(x8) device receive 14/10/3 addressing. The 1Gb
DDR2 device operates with a single 1.8V ± 0.1V power supply and 1.8V ± 0.1V VDDQ.
The 1Gb DDR2 device is available in 60ball FBGA(x8) and 84ball FBGA(x16).
Features:
• JEDEC standard VDD = 1.8V ± 0.1V Power Supply
• VDDQ = 1.8V ± 0.1V
• 533MHz fCK for 1066Mb/sec/pin
• 8 Banks
• Posted CAS
• Programmable CAS Latency: 4, 5, 6, 7
• Programmable Additive Latency: 3, 4, 5. 6
• Write Latency(WL) = Read Latency(RL) -1
• Burst Length: 4 , 8(Interleave/nibble sequential)
• Programmable Sequential / Interleave Burst Mode
• Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature)
• Off-Chip Driver(OCD) Impedance Adjustment
• On Die Termination
• Special Function Support - PASR(Partial Array Self Refresh) - 50ohm ODT - High
Temperature Self-Refresh rate enable
• Average Refresh Period 7.8us at lower than TCASE 85°C, 3.9us at 85°C < TCASE < 95
°C
• All of products are Lead-free, Halogen-free, and RoHS compliant
8.2 Features
8.1 General Description
38
LC-22LE240
Pinning:
8.3 Pinning
39
LC-22LE240
9. SCALER AND LVDS SOCKETS
9.1.LVDS sockets Block Diagram
9.2. Panel Supply Switch Circuit
This switch is used to open and close panel supply of TCON. It is controlled by port of
main ucontroller. Also with this circit panel sequency could be adjusted correctly. 3 panel
supplys are connected to this circuit. All of them are optional according to panels.
40
LC-22LE240
AVDD2V5_REF
AVDD2V5_AUD
AVDD2V5_MOD
F305
1k
F307
1k
1k
F308
100nF
16V
16V
C1221
12V_VCC
12V_VCC/STBY
12V_STBY
12V_VCC
16V
100nF
C1222
C69
1uF
50V
1uF
50V
220uF
C65
10V
3V3_VCC
3V3_STBY
S8
S7
VDD_AUDIO_PWR
VDD_AUDIO_PWR
12V_STBY
12V_VCC/STBY
S10
S19
S21
S22
1uF
C1128
25V
CN706
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
10k
R1685
1
2
3V3_VCC
4k7
R1678
1
2
R1679
100R
100R
R1973
3V3_VCC
DIMMING
BACKLIGHT_ON/OFF
5V_STBY
5V_VCC
STBY_ON/OFF
16V
100nF
C1022
1k
F306
6V3
10uF
C1081
F272
60R
BC848B
Q194
1
2
3
Q193
BC858B
BC858B
1
2
3
Q211
BC848B
1
2
3
60R
F302
1
2
3V3_VCC
4k7
R1748
1
2
BC848B
Q188
1
2
3
MSD9WB9PT-2
U5
H15
H16
H17
J14
J15
J16
J17
H14
K14
N7
N8
P7
P8
T8
R7
R8
U8
V8
E8
F8
G8
G9
E9
F9
J8
H8
G16
G17
G15
E15
E16
E17
F16
F17
K9
L9
M9
N9
P9
R9
D10
E10
F10
G10
H10
J10
K10
L10
M10
N10
P10
R10
D11
E11
F11
G11
H11
J11
K11
L11
M11
N11
P11
R11
D12
E12
F12
G12
H12
J12
K12
L12
M12
N12
P12
R12
D13
E13
F13
G13
H13
J13
K13
L13
M13
N13
P13
R13
D14
E14
L14
M14
N14
P14
R14
D15
K15
L15
M15
N15
P15
R15
D16
K16
L16
M16
D17
K17
L17
M17
K18
L18
M18
W2
W3
V4
V5
V6
D9
D18
GND87
GND86
GND85
GND84
GND83
GND82
GND81
GND80
GND79
GND78
GND77
GND76
GND75
GND74
GND73
GND72
GND71
GND70
GND69
GND68
GND67
GND66
GND65
GND64
GND63
GND62
GND61
GND60
GND59
GND58
GND57
GND56
GND55
GND54
GND53
GND52
GND51
GND50
GND49
GND48
GND47
GND46
GND45
GND44
GND43
GND42
GND41
GND40
GND39
GND38
GND37
GND36
GND35
GND34
GND33
GND32
GND31
GND30
GND29
GND28
GND27
GND26
GND25
GND24
GND23
GND22
GND21
GND20
GND19
GND18
GND17
GND16
GND15
GND14
GND13
GND12
GND11
GND10
GND9
GND8
GND7
GND6
GND5
GND4
GND3
BYPASS
AVDD_DDR_4
AVDD_DDR_3
AVDD_DDR_2
AVDD_DDR_1
AVDD_DDR_0
AVDD_LPLL
VDDP1
VDDP0
AVDD_EAR33
AVDD_AU33
AVDD_CVBS33_1
AVDD_CVBS33_0
AVDD_DMPLL
AVDD_ALIVE_2
AVDD_ALIVE_1
AVDD_ALIVE_0
PGA_VCOM
AVDD_PGA25
AVDD_MOD25_1
AVDD_MOD25_0
AVDD_AU25
AVDD_REF25_1
AVDD_REF25_0
AVDD_ADC25_1
AVDD_ADC25_0
AVDD_126
DVDD_DDR
VDDC6
VDDC5
VDDC4
VDDC3
VDDC2
VDDC1
VDDC0
6
12V_VCC
L2
10uH
R18
10k
4k7
R41
2k2
R42
Ulas Dereli
POWER_1&LNBP
8
17mb62-
2
8
7
6
5
4
3
2
1
A
B
C
D
E
F
A X M
1
2
3
4
5
6
7
8
A
B
C
D
E
F
OF:
A3
PROJECT NAME :
VESTEL
SCH NAME :
DRAWN BY :
SHEET:
25-08-2011_15:27
VDDC_1V2
C68
50V
15nF
15k
R43
C12
220nF
25V
D7
1N4001
LNB_OUT
C70
470nF
25V
470nF
25V
3V3_VCC
R19
10k
F295
1k
SK24
D8
C13
220nF
25V
16V
C997
100nF
100nF
SDA_SYS
SCL_SYS
SCL_SYS
3V3_VCC
100nF
16V
16V
C1005
C14
25V
220nF
C1070
16V
100nF
C1004
16V
100nF
LNBH23L
U6
27
4
19
18
18
6
9
9
14
29
30
29
30
22
13
21
11
12
13
21
11
12
1
2
3
7
8
2
3
7
8
16
17
23
24
25
26
31
32
17
23
24
25
26
31
32
10
15
28
5
20
A_GND
P_GND
I_SEL
BYP
ADDR
NC_13
NC_12
NC_11
NC_10
NC_9
NC_8
NC_7
NC_6
NC_5
NC_4
NC_3
NC_2
NC_1
DSQIN
PDC
VO_RX
EXTM
VO_TX
RSV_2
RSV_1
TTX
SCL
SDA
VCC_L
VCC
LX
V_UP
12V_VCC
S82
1
2
R1636
10k
1
2
10k
R1635
1
2
3V3_TUNER
12V_VCC
3V3_VCC
VDD_3V3
1N5819
D6
5V_VCC
DISEQC_OUT
R1750
22k
VDD_AUDIO_PWR
10k
R1631
1
2
16V
100nF
C1009
10uF
10V
10V
C774
C974
1uF
6V3
6V3
AVDD_DDR
AVDD_3V3
AVSS_PGA
AVDD_2V5_PGA
AVDD2V5_ADC
BAW56
D184
1
2
3
10k
R1639
1
2
BC848B
Q191
1
2
3
STBY_ON/OFF
3V3_STBY
STBY_ON/OFF_NOT
10k
R1638
1
2
Q178
BC848B
1
2
3
Q180
BC858B
1
2
3
3V3_STBY
R1649
33k
1
2
D185
BAW56
1
2
3
D186
BAW56
1
2
3
100nF
C971
10V
1
2
PROTECT
TP202
1
U7
LM809
1
3
2
RST
VCC
GND
3V3_STBY
R1761
100R
1
2
3
4
5
6
7
8
R4
R1
R3
R2
R1166
4k7
1
2
50V
C840
220pF
1
2
3V3_VCC
4k7
R1158
1
2
BACKLIGHT_DIM
DIMMING
C839
50V
220pF
1
2
50V
220pF
C838
1
2
4k7
R1165
1
2
R1221
1k
1
2
S18
MEGA_DCR_IN
S16
MEGA_DCR_OUT
12V_STBY
S17
Q189
BC848B
BC848B
1
2
3
F277
60R
R20
10k
10k
1
2
R40
20k
20k
10k
R21
R1727
33k
1
2
100nF
C1025
16V
C1024
100nF
16V
100nF
16V
3V3_STBY
VDDC_1V2
16V
C1001
100nF
C1029
10uF
6V3
10uF
6V3
AVDD_2V5_PGA
10uF
C1030
6V3
C1028
6V3
10uF
AVDD_DDR
F270
60R
AVSS_PGA
100nF
16V
16V
C1008
2V5_VCC
F271
60R
3V3_VCC
60R
F274
100nF
C1007
16V
1V8_VCC
1V2_VCC
C1014
16V
100nF
2V5_VCC
VDD_3V3
AVDD_3V3
PANEL_VCC_ON/OFF
PANEL_VCC
F290
60R
1
2
47R
R1725
1
2
33k
R1734
1
2
22k
R1749
FDC642P
Q199
1
3
4
5
6
2
TP213
1
F288
60R
1
2
F289
60R
1
2
10k
R1693
1
2
C1042
100nF
100nF
10V
1
2
5V_VCC
12V_VCC
Q190
BC848B
BC848B
1
2
3
5V_VCC
C7
16V
22uF
12V_VCC/STBY
12V_VCC/STBY
5V_STBY
LM1117
U1
1
2
3
4
VOUT
IN
OUT
ADJ
3V3_STBY
12V_VCC/STBY
22uF
6V3
6V3
C990
R1677
4k7
1
2
R1676
4k7
1
2
C6
16V
22uF
16V
100nF
C1223
100nF
16V
16V
C1224
C1225
100nF
16V
100nF
16V
AVDD2V5_ADC
AVDD2V5_REF
AVDD2V5_AUD
AVDD2V5_MOD
DIMMING CIRCUIT
AP211H
SHORT CCT PROTECTION
LNB CIRCUIT
PANEL SUPPLY SWITCH
60R 402 ferrite secilecek
POWER SOCKET
PW04 LOW POWER Option
NC
NC
ADAPTOR OVER VOLTAGE PROTECTION
NC
10. SPI FLASH MEMORY - MX25L1005 (U158)
10.1. General Description
MX25L1005 is a CMOS 1,048,576 bit serial Flash memory, which is configured as
131,072 x 8 internally.The MX25L1005 feature a serial peripheral interface and software
protocol allowing operation on a simple 3-wire bus. The three bus signals are a clock
input (SCLK), a serial data input (SI), and a serial data output (SO). SPI access to the
device is enabled by CS# input. The MX25L1005 provide sequential read operation on
whole chip. After program/erase command is issued, auto program/ erase algorithms
which program/ erase and verify the specified page or sector/block locations will be
executed. Program command is executed on page (256 bytes) basis, and erase
command is executes on chip or sector(4K-bytes) or block(64K-bytes). To provide user
with ease of interface, a status register is included to indicate the status of the chip. The
status read command can be issued to detect completion status of a program or erase
operation via WIP bit. When the device is not in operation and CS# is high, it is put in
standby mode and draws less than 10uA DC current. The MX25L1005 utilize MXIC's
proprietary memory cell, which reliably stores memory contents even after 100,000
program and erase cycles.
10.2. Features
Serial Peripheral Interface (SPI) compatible -- Mode 0 and Mode 3
1,048,576 x 1 bit structure
32 Equal Sectors with 4K byte each, Any Sector can be erased individually
2 Equal Blocks with 64K byte each, Any Block can be erased individually
Single Power Supply Operation
3V3 or 5V
or 12V
or 12V
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