Sharp LC-19A1E (serv.man5) Service Manual ▷ View online
LC-19A1E-BK/WH
5 – 13
19
P2_4
L_R
O
Right and left reversing signal
OPEN
20
P2_3
U_D
O
Upper and lower reversing signal
OPEN
21
P2_2
SYNC_DET
O
PC Power Management Setting
OPEN
22
P2_1
PC-V
I
PC Signal Vertical Sync Frequency Judgement
PC-V
23
P2_0
PC-H
I
PC Signal Horizontal Sync Frequency Judgement
PC-H
24
P1_7
PC_WARKUP
I
Detecting Existence of PC Signal Vertical Signal
PC-WARKUP
25
P1_6
RS_ON
O
Power control signal for RS232C IC
RS-ON
26
P1_5
RXD0
I
no connection
OPEN
27
P1_4
TXD0
O
no connection
OPEN
28
P8_6
IR_PASS
O
Remote Control Signal External Through Switching
IREM_SW
29
P8_5
CTRL1 (POWout)
O
Power control signal (for Q701)
POW
30
P8_4
POWIN
I
DC/DC Startup Detection
B3.3V
31
P8_3
CTRL2
(DVP33_CTRL)
(DVP33_CTRL)
O
DVP3.3V Power Control signal Output
OPEN
32
P8_2
DVP15_IN
I
Detecting DVP1.5V Power Supply
B1.5V
33
P8_12
MRDY(L)
I
Bus Opening for Process (L=bus open)
OPEN
34
P8_0
EEP_STOP_O
O
Control signal that prohibits accessing common EEPROM
E2P-STOP
35
P6_0
AC_CTL
O
Power Unit Control signal (SLEEP Mode)
AC-CTL
36
P4_5
IREM1(RC)
I
Remote Control Input
R/C
37
P6_6
TXD1
O
Transmitted Data signal (at RS232C/includes for process)
TXD
38
P6_7
RXD1
I
Received Data signal (at RS232C/includes for process)
RXD
39
P6_5
DVP_CS
O
DVP-M2 Microcomputer Communication (Chip Enable)
DVP-INT
40
P6_4
DVP_TXD2
I
DVP-M2 Microcomputer Communication (DATA Signal Input)
DVP-TXD
41
P6_3
DVP_RXD2
O
Communication signal between DVP-M2 and microcomputer
(DATA Signal Output)
(DATA Signal Output)
DVP-RXD
42
P3_1
DDC_RESET
O
Image Relation IC Reset Output (DVP-M2)
DDC_RESET
43
P3_0
SDAO
I/O
I2C CH0 SDA (EEPROM (For POWER))
SDA
44
P3_6
SCLO
I
I2C CH0 SCL (EEPROM (For POWER))
SCL
45
P3_2
DVP_REQ
O
Communication signal between DVP-M2 and microcomputer
(Demands Communication)
(Demands Communication)
DVP-REQ
46
P1_3
POW_SW
I
Main power switch control signal
STB POW
47
P1_2
KEY 1
I
Main Unit Key Input 1
OPEN
48
P1_1
KEY 2
I
Main Unit Key Input 2
OPEM
49
P1_0
PSIZ_H
I
Mounting distinction (Panel size)
BU3.3V
50
P0_0
AREA
I
Mounting distinction (Destination)
REGION
51
P0_1
(QSTEMP)
I
Thermistor Input (Panel Temperature)
OPEN
52
P0_2
(FRAME)
O
QS Drive Bank Switching (50/60Hz)
OPEN
53
P0_3
(QS_ON)
O
QS Drive ON/OFF signal
OPEN
54
P0_4
(QS_TEMP 1)
O
QS Drive Temperature Control 1
OPEN
55
P6_2
(QS_TEMP 2)
O
QS Drive Temperature Control 2
OPEN
56
P6_1
(QS_TEMP 3)
O
QS Drive Temperature Control 3
OPEN
57
P0_5
(OPC)
I
Brightness Censer Input
OPEN
58
P0_6
VBRT
O
Dimming Control (Analogue Dimming)
VBRT
59
VSS
-
Ground.
Ground
60
P0_7
COM_BIAS
O
Output signal for common bias adjustment
CS_ADD
61
VREF
-
A/D,D/A Converter Standard Voltage Input signal
V REF
62
VCC
-
Power Supply Input
BU3.3V
63
P3_7
(U_D)
O
Upper and lower reversing signal
OPEN
64
P3_5
SCL 1
I
I2C CH1 clock (E2PROM)
SCL 1
Pin No.
Port
Pin Name
I/O
Pin Function
Seet Name
LC-19A1E-BK/WH
5 – 14
2.5. IC2003 (VHiBR24L04F-1Y)
2.5.1 Block Diagram
2.5.2 Pin Connections and short description
Pin No.
Pin Name
I/O
Pin Function
1
A0
-
No Connection
2
A1
I
Address input A1
3
A2
I
Address input A2
4
GND
-
Ground.
5
SDA
I/O
Serial Address Data.
6
SCL
I
Serial Clock
7
WP
I
Write protect input pin.
8
VCC
-
Power Supply
LC-19A1E-BK/WH
5 – 15
2.6. IC9201 (RH-iXC209WJZZQ)
2.6.1 Block Diagram
LC-19A1E-BK/WH
5 – 16
2.6.2 Pin Connections and short description
Pin No.
Pin Name
I/O
Pin Function
Input interface
5
5
RA-
I
LVDS Input signal.
6
RA+
I
LVDS Input signal
7
RB-
I
LVDS Input signal
8
RB+
I
LVDS Input signal
10
RC-
I
LVDS Input signal
11
RC+
I
LVDS Input signal
14
RD-
I
LVDS Input signal
15
RD+
I
LVDS Input signal
12
RCLK-
I
LVDS clock signal
13
RCLK+
I
LVDS clock signal
23
SELLVDS
I
Mapping switch terminal
24
HSCAN
I
Right and left reversing selecting terminal
25
VSCAN
I
Upper and lower reversing selecting terminal
Source driver output signal.
53
53
RSR0N
O
RSDS [R] DATA output signal.
54
RSR0P
O
RSDS [R] DATA output signal.
55
RSR1N
O
RSDS [R] DATA output signal.
56
RSR1P
O
RSDS [R] DATA output signal.
57
RSR2N
O
RSDS [R] DATA output signal.
58
RSR2P
O
RSDS [R] DATA output signal.
59
RSCKN
O
RSDS Clock signal.
60
RSCKP
O
RSDS Clock signal.
61
RSG0N
O
RSDS [G] DATA output signal.
62
RSG0P
O
RSDS [G] DATA output signal.
63
RSG1N
O
RSDS [G] DATA output signal.
64
RSG1P
O
RSDS [G] DATA output signal.
65
RSG2N
O
RSDS [G] DATA output signal.
66
RSG2P
O
RSDS [G] DATA output signal.
67
RSB0N
O
RSDS [B] DATA output signal.
68
RSB0P
O
RSDS [B] DATA output signal.
69
RSB1N
O
RSDS [B] DATA output signal.
70
RSB1P
O
RSDS [B] DATA output signal.
71
RSB2N
O
RSDS [B] DATA output signal.
72
RSB2P
O
RSDS [B] DATA output signal.
47
LS
O
Latch signal.
44
SSP1
O
Start pulse 1
79
SSP2
O
Start pulse 2
45
REV
O
Polarity reversing terminal
46
REV2
O
Polarity reversing terminal 2
48
LBR
O
Source driver upper and lower/right and left reversing setting
49
LBRB
O
Reversing output of LBR
50
FS
O
Frame signal for offset cancellation
Gate driver output signal.
37
37
GCK
O
Gate driver clock
36
GSP1
O
Gate start pulse 1
35
GSP2
O
Gate start pulse 2
38
GOE
O
Gate output enable signal
40
RL
O
The terminal for upper and lower/right and left reversal setting of a gate driver
39
RLB
O
Reversing output of RL
Others
100
100
GRST
I
Gate array reset terminal
75
REXT
I
RSDS current adjustment terminal
Setting terminal
27
27
REVMODE
I
Reversing drive method selecting terminal
97
MODE1
I
Resolution selecting terminal 1
98
MODE2
I
Resolution selecting terminal 2
99
MODE3
I
Resolution selecting terminal 3
95
LMD1
I
LMD pattern selecting terminal 1
96
LMD2
I
LMD pattern selecting terminal 2
93
LMDSEL1
I
The terminal 1 for selection of the reversal drive system of LMD
94
LMDSEL2
I
The terminal 2 for selection of the reversal drive system of LMD
3
BIST
I
BIST operation selecting terminal
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