Sharp 76GF-63 (serv.man2) Service Manual ▷ View online
DA100 (50Hz) Chassis – Article for Television Magazine
Page 57 of 80
Sharp Electronics (UK) Limited - March 2003
Revision 2
Input Selector
Up to five analogue inputs can be connected. Four inputs are for composite video or S-VHS luminance
signal. These inputs are clamped to the sync back porch and are amplified by a variable gain amplifier.
One of these inputs is for connection of S-VHS chrominance signal (it is internally biased and has a
fixed gain amplifier).
signal. These inputs are clamped to the sync back porch and are amplified by a variable gain amplifier.
One of these inputs is for connection of S-VHS chrominance signal (it is internally biased and has a
fixed gain amplifier).
Clamping
The composite video input signals are AC coupled to the IC. The clamping voltage is stored on the
coupling capacitors and is generated by digitally controlled current sources. The clamping level is
referenced to the back porch of the video signal. S-VHS chrominance is also AC coupled. The input pin
is internally biased to the centre of the Analogue to Digital Converter input range.
coupling capacitors and is generated by digitally controlled current sources. The clamping level is
referenced to the back porch of the video signal. S-VHS chrominance is also AC coupled. The input pin
is internally biased to the centre of the Analogue to Digital Converter input range.
Automatic Gain Control
A digitally working automatic gain control adjusts the magnitude of the selected base-band by +6/–
4.5dB in 64 logarithmic steps to the optimal range of the Analogue to Digital Converter. The gain of
the video input stage including the Analogue to Digital Converter is 213 steps/V with the AGC set to
0dB.
4.5dB in 64 logarithmic steps to the optimal range of the Analogue to Digital Converter. The gain of
the video input stage including the Analogue to Digital Converter is 213 steps/V with the AGC set to
0dB.
Analogue to Digital Converters
Two Analogue to Digital Converters are provided to digitise the input signals. Each converter runs with
20.25 MHz and has 8-bit resolution. An integrated band-gap circuit generates the required reference
voltages for the converters.
20.25 MHz and has 8-bit resolution. An integrated band-gap circuit generates the required reference
voltages for the converters.
Digitally Controlled Clock Oscillator
The clock generation is also a part of the analogue front end. The crystal oscillator is controlled
digitally by the control processor; the clock frequency can be adjusted within ±150 ppm.
digitally by the control processor; the clock frequency can be adjusted within ±150 ppm.
Analogue Video Output
The input signal of the luminance Analogue to Digital Converter is available at the analogue video
output pin. A source follower must buffer the signal at this pin. The output voltage is 2V, thus the
signal can be used to drive a 75Ω line. The magnitude is adjusted with an AGC in 8 steps together with
the main AGC.
output pin. A source follower must buffer the signal at this pin. The output voltage is 2V, thus the
signal can be used to drive a 75Ω line. The magnitude is adjusted with an AGC in 8 steps together with
the main AGC.
Average Beam Current Limiting
The average beam current limiter (BCL) uses the sense input for the beam current measurement. The
BCL uses a different filter to average the beam current during the active picture. The filter
bandwidth is approximately 2kHz.
The beam current limiter has an automatic offset adjustment that is active two lines before the first
cut-off measurement line and allows the setting of a threshold current. If the beam current is above
the threshold, the excess current is low-pass filtered and used to attenuate the RGB outputs by
adjusting the white-drive multipliers for the internal (digital) RGB signals, and the analogue contrast
multipliers for the analogue RGB inputs, respectively.
The lower limit of the attenuator is programmable, thus a minimum contrast can always be set. During
the CRT measurement, the ABL attenuation is switched off. This is why some faults are ‘masked in
the service mode. After the white drive measurement line, it takes 3 lines to switch back to BCL
limited drives and brightness.
BCL uses a different filter to average the beam current during the active picture. The filter
bandwidth is approximately 2kHz.
The beam current limiter has an automatic offset adjustment that is active two lines before the first
cut-off measurement line and allows the setting of a threshold current. If the beam current is above
the threshold, the excess current is low-pass filtered and used to attenuate the RGB outputs by
adjusting the white-drive multipliers for the internal (digital) RGB signals, and the analogue contrast
multipliers for the analogue RGB inputs, respectively.
The lower limit of the attenuator is programmable, thus a minimum contrast can always be set. During
the CRT measurement, the ABL attenuation is switched off. This is why some faults are ‘masked in
the service mode. After the white drive measurement line, it takes 3 lines to switch back to BCL
limited drives and brightness.
Protection Circuitry
‘Vertical fly-back’ and the ‘Safety’ inputs provide picture tube and drive stage protection.
Vertical fly-back; This pin searches for a negative edge in every field, otherwise the RGB drive signals
Vertical fly-back; This pin searches for a negative edge in every field, otherwise the RGB drive signals
DA100 (50Hz) Chassis – Article for Television Magazine
are blanked. This feature can be selected by software.
The safety input pin has two thresholds. Between zero and the lower threshold, normal functioning
takes place. Between the lower and the higher threshold, the RGB signals are blanked. Above the
higher threshold, the RGB signals are blanked and the horizontal drive is shut off.
Both thresholds have a small amount of hysteresis. The main oscillator and the horizontal drive
circuitry are run from a separate (standby) power supply and are already active while the television is
powering up.
Note that in this chassis the standby supply pin is connected to VCC.
The safety input pin has two thresholds. Between zero and the lower threshold, normal functioning
takes place. Between the lower and the higher threshold, the RGB signals are blanked. Above the
higher threshold, the RGB signals are blanked and the horizontal drive is shut off.
Both thresholds have a small amount of hysteresis. The main oscillator and the horizontal drive
circuitry are run from a separate (standby) power supply and are already active while the television is
powering up.
Note that in this chassis the standby supply pin is connected to VCC.
Scan Velocity Modulation Output
This output delivers the analogue SVM signal. The Digital to Analogue Converter is a current sink like
the RGB Digital to Analogue Converters. At zero signal level the output current is 50% of the maximum
output current.
the RGB Digital to Analogue Converters. At zero signal level the output current is 50% of the maximum
output current.
Protection – Video/Sync Processor
The video/sync processor (IC801) contains protection circuit that can monitor the scanning circuits
operation.
operation.
Safety
On pin 12 of IC801, EHT is calculated by measuring the rectified horizontal fly-back pulse. D615 and
C617 rectify and smooth this supply, D617 limits the bias at pin 12 (under normal conditions this
voltage is less than 1V). There are two thresholds once the first threshold has been met the RGB
drives are blanked. If the D.C. voltage continues to rise and passes the second threshold, then the
horizontal drive is stopped so that forward X-rays are not emitted.
C617 rectify and smooth this supply, D617 limits the bias at pin 12 (under normal conditions this
voltage is less than 1V). There are two thresholds once the first threshold has been met the RGB
drives are blanked. If the D.C. voltage continues to rise and passes the second threshold, then the
horizontal drive is stopped so that forward X-rays are not emitted.
Vertical Protection (VPROT)
This pin monitors the operation of the vertical output stage. The vertical fly-back pulses are applied
to pin 11 (this is a 50Hz, 5V peak pulse). This signal is taken from the vertical flyback generator
circuit (Q502 and Q503). If the negative edge of this signal cannot be detected then the RGB drives
are blanked.
to pin 11 (this is a 50Hz, 5V peak pulse). This signal is taken from the vertical flyback generator
circuit (Q502 and Q503). If the negative edge of this signal cannot be detected then the RGB drives
are blanked.
Figure 56: VDP Protection Circuits
Page 58 of 80
Sharp Electronics (UK) Limited - March 2003
Revision 2
DA100 (50Hz) Chassis – Article for Television Magazine
Faults Connected to the VDP
In later versions of this chassis a slightly different version of VDP was fitted. The type number
(VDP3120) is the same, but the revision number is different. If patterning is experienced after
changing IC801 (VDP3120 only), remove C824 if fitted. This capacitor is fitted from pin 33 of IC801
to ground.
(VDP3120) is the same, but the revision number is different. If patterning is experienced after
changing IC801 (VDP3120 only), remove C824 if fitted. This capacitor is fitted from pin 33 of IC801
to ground.
Figure 57: Position of C824
Note that poor dressing of the cables can also cause patterning.
Two types of VDP have been fitted to the chassis and they are not compatible. Make sure that the
correct type is fitted – VDP3120 or VDP3130 (see the IC table at the start of this article for more
details on IC801 types).
Two types of VDP have been fitted to the chassis and they are not compatible. Make sure that the
correct type is fitted – VDP3120 or VDP3130 (see the IC table at the start of this article for more
details on IC801 types).
Page 59 of 80
Sharp Electronics (UK) Limited - March 2003
Revision 2
DA100 (50Hz) Chassis – Article for Television Magazine
Picture Rotation
Due to the width of a 16:9 CRT the horizontal tilt of the picture can be influence by external magnetic
fields. To overcome this problem, an extra coil is fitted around the CRT, which is connected to a DC
amplifier, controlled by the microprocessor.
fields. To overcome this problem, an extra coil is fitted around the CRT, which is connected to a DC
amplifier, controlled by the microprocessor.
Figure 58: Picture Rotation Circuit (located on CRT PWB)
Circuit Description
The microprocessor (IC1001) will output a PWM signal from pin 55. This signal is then passed through
a LPF comprising of R1620 and C1608 and fed to an error amplifier (IC1601). The output from this
error amp can swing from a positive to a negative voltage depending on the mark space ratio of the
PWM signal from IC1001.
Under normal conditions (CRT is not effected by external magnetic fields) there will be no output
from the error amplifier, therefore, both Q1603 and Q1604 are turned off causing no current to flow
through the coil around the CRT neck. However if the output from the error amplifier is positive then
Q1603 will turn on allowing current to flow from the +13V rail, through the coil to ground. If the error
amplifier output is negative going then Q1604 will turn on, allowing current to flow from ground to the
–13V rail.
The end user has control of this adjustment via the picture menu.
Notes
a LPF comprising of R1620 and C1608 and fed to an error amplifier (IC1601). The output from this
error amp can swing from a positive to a negative voltage depending on the mark space ratio of the
PWM signal from IC1001.
Under normal conditions (CRT is not effected by external magnetic fields) there will be no output
from the error amplifier, therefore, both Q1603 and Q1604 are turned off causing no current to flow
through the coil around the CRT neck. However if the output from the error amplifier is positive then
Q1603 will turn on allowing current to flow from the +13V rail, through the coil to ground. If the error
amplifier output is negative going then Q1604 will turn on, allowing current to flow from ground to the
–13V rail.
The end user has control of this adjustment via the picture menu.
Notes
The location of this circuit can vary between 66cm models (located on CRT base) and 76cm models
(located on sub PWB).
(located on sub PWB).
The circuit is not fitted on the HW series of televisions or the 56FW53H.
Page 60 of 80
Sharp Electronics (UK) Limited - March 2003
Revision 2
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