Sharp 76DW-18H (serv.man3) Service Manual ▷ View online
Wide Screen, Colour Television CW100 Chassis
Sharp Electronics (UK) Ltd
Technical Support
February 99
Page 21
SYNC PROCESSOR
This IC is located on the 100Hz PWB circuit reference is IC6110. As its name implies it is responsible
for processing Vertical & Horizontal synchronisation signals. However, since the CW100 has a filed
scanning rate of 100Hz both the Vertical & Horizontal frequencies are twice that of a CTV with 50Hz
field scan. The Key features of this IC are:
for processing Vertical & Horizontal synchronisation signals. However, since the CW100 has a filed
scanning rate of 100Hz both the Vertical & Horizontal frequencies are twice that of a CTV with 50Hz
field scan. The Key features of this IC are:
Deflection - Protection - 16:9 / 4:3
Three selectable reduced V-scan modes (75 %, 66 %, 50 % V-size)
Adjustable over-scan to hide the cut off control measuring lines in the reduced scan modes
Stop/start of vertical deflection adjustable to fill out the 16/9 screen with different letterbox
formats without annoying over-scan
Adjustable over-scan to hide the cut off control measuring lines in the reduced scan modes
Stop/start of vertical deflection adjustable to fill out the 16/9 screen with different letterbox
formats without annoying over-scan
I
2
C Bus alignment of all parameters
East/West-functions
Independent adjustment of
Upper/lower corner
V-angle correction:
V-bow correction
V-angle correction:
V-bow correction
Picture Width & Height compensation for fluctuation of EHT
H- and V-blanking time adjustable
Protection against EHT runaway (X-rays protection)
Protection against missing V-deflection (CRT-protection)
Soft-start of the H-output stage
H- and V-blanking time adjustable
Protection against EHT runaway (X-rays protection)
Protection against missing V-deflection (CRT-protection)
Soft-start of the H-output stage
D
ESCRIPTION
The SDA 9362 is a highly integrated deflection controller for CTV receivers with doubled line and
standard or doubled field frequencies. It controls among others a horizontal driver circuit line output
stage, a DC coupled vertical sawtooth output stage and an East-West raster correction circuit. All
adjustable output parameters are I
standard or doubled field frequencies. It controls among others a horizontal driver circuit line output
stage, a DC coupled vertical sawtooth output stage and an East-West raster correction circuit. All
adjustable output parameters are I
2
C Bus controlled. Inputs are HSYNC, VSYNC and the line locked
clock (CLL).
The output signals will control the horizontal as well as the vertical deflection stage including the East-
West raster correction circuit. The H-output signal ‘HD’ compensates the delays of the line output
stage and its phase can be modulated by the vertical frequency to remove horizontal distortions of the
vertical raster lines (V-Bow, V-Angle). A positive HD pulse switches off the line output transistor.
West raster correction circuit. The H-output signal ‘HD’ compensates the delays of the line output
stage and its phase can be modulated by the vertical frequency to remove horizontal distortions of the
vertical raster lines (V-Bow, V-Angle). A positive HD pulse switches off the line output transistor.
The V-output sawtooth signals VD- (Vertical A) and VD+ (Vertical B) controls a DC coupled class D
output stage. The East-West output signal E/W is a vertical frequency parabola of 4th order, enabling
an additional corner correction, separately for the upper and lower part.
output stage. The East-West output signal E/W is a vertical frequency parabola of 4th order, enabling
an additional corner correction, separately for the upper and lower part.
The picture width and height compensation processes is controlled by the IBEAM signal, this will
effect the E/W and VD signal, enabling constant width and height independent of brightness.
effect the E/W and VD signal, enabling constant width and height independent of brightness.
The start up-circuit controls the energy supply to the H-output stage during the receiver's run up time
by smoothly decreasing the line output transistors switching frequency down to the normal operating
value (soft-start). HD starts with about 55 kHz and decreases within 85 ms to its final value of
31.25kHz. A watch dog function limits the period of the HD output signal independent of the clock CLL
to a max 35.2
by smoothly decreasing the line output transistors switching frequency down to the normal operating
value (soft-start). HD starts with about 55 kHz and decreases within 85 ms to its final value of
31.25kHz. A watch dog function limits the period of the HD output signal independent of the clock CLL
to a max 35.2
µ
s.
The protection circuit watches an EHT reference and the sawtooth of the vertical output stage. H-
output stage is switched off if the EHT succeeds a defined threshold or if the V-deflection fails. The
function of this circuit is based on the internal quartz oscillator and therefore independent of the input
clock CLL.
output stage is switched off if the EHT succeeds a defined threshold or if the V-deflection fails. The
function of this circuit is based on the internal quartz oscillator and therefore independent of the input
clock CLL.
HPR0T
Vi < V2
Continues blanking
Vi > V1
HD disabled
V2
≤
Vi < V1
Operating range
Wide Screen, Colour Television CW100 Chassis
Sharp Electronics (UK) Ltd
Technical Support
February 99
Page 22
VPROT:
Vertical saw-tooth voltage
Vi < V1 in first half of V-period or
Vi > V2 in second half: HD disabled
Vi < V1 in first half of V-period or
Vi > V2 in second half: HD disabled
The pin SCP (Sandcastle) delivers the composite blanking signal SCP. It contains burst (
Vb ), H-
blanking HBL (
VHBL ) V-blanking. The phase of the H-blanking period can be varied by I
2
C Bus.
The system clock for the SDA 9362 has to be generated externally and is applied to pin1 'CLL'. Its
frequency must be always be the same as the line frequency (defined by the horizontal time reference
HSYNC) multiplied by 864. If no HSYNC signal is available an internal horizontal synchronization
signal is derived from CLL (CLL divided by 879).
frequency must be always be the same as the line frequency (defined by the horizontal time reference
HSYNC) multiplied by 864. If no HSYNC signal is available an internal horizontal synchronization
signal is derived from CLL (CLL divided by 879).
The input signal at VSYNC is the vertical time reference. It has to pass a window avoiding too short or
long V-periods in the case of distorted or missing VSYNC pulses. The window allows a VSYNC pulse
only after a minimum number of lines from its predecessor and sets an artificial one after a maximum
number of lines. The window size is programmable by I
long V-periods in the case of distorted or missing VSYNC pulses. The window allows a VSYNC pulse
only after a minimum number of lines from its predecessor and sets an artificial one after a maximum
number of lines. The window size is programmable by I
2
C Bus.
The beam-current dependent input signal IBEAM is A/D converted and then digitally processed. The
A/D Converter requires a clock frequency twice the frequency of CLL. This is generated by an internal
analog PLL with an external loop filter at pin LF. Values, which influence shape and amplitude of the
output signals, are transmitted as reduced binary values to the SDA 9362 via I
A/D Converter requires a clock frequency twice the frequency of CLL. This is generated by an internal
analog PLL with an external loop filter at pin LF. Values, which influence shape and amplitude of the
output signals, are transmitted as reduced binary values to the SDA 9362 via I
2
C Bus. A CPU which is
designed for speed reasons in a pipe line structure calculates in consideration of feedback signals
(e.g. IBEAM) values which exactly represent the output signals. These values control after D/A
conversion the external deflection and raster correction circuits. The CPU firmware is stored in an
internal ROM.
(e.g. IBEAM) values which exactly represent the output signals. These values control after D/A
conversion the external deflection and raster correction circuits. The CPU firmware is stored in an
internal ROM.
Figure 1 Sync Processor Block Diagram
Wide Screen, Colour Television CW100 Chassis
Sharp Electronics (UK) Ltd
Technical Support
February 99
Page 23
Self Assessment Question
If VPROT goes permanently high, what is the effect?
How is soft start of the horizontal output stage achieved?
Wide Screen, Colour Television CW100 Chassis
Sharp Electronics (UK) Ltd
Technical Support
February 99
Page 24
16:9 Picture Format
20 Min Study Period
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