Sharp 76DW-18H (serv.man3) Service Manual ▷ View online
Wide Screen, Colour Television CW100 Chassis
Sharp Electronics (UK) Ltd
Technical Support
February 99
Page 17
F
IELD
S
TORE
There are two versions of the CW100 chassis 100Hz PWB, the difference is in the Field Store. The
early 100Hz PWB's used 6, SDA9251 (triple port, Dynamic Sequential Access Memory). Each port is
4 bit wide and has a memory of 868352-Bit. This means that to store a field of picture data three
device is required. To store both odd & even fields, 6 SDA9251 are required.
early 100Hz PWB's used 6, SDA9251 (triple port, Dynamic Sequential Access Memory). Each port is
4 bit wide and has a memory of 868352-Bit. This means that to store a field of picture data three
device is required. To store both odd & even fields, 6 SDA9251 are required.
Later production of the 100Hz PWB (This is the one that you are more likely to find fitted) the 6 x
SDA9251 has been replaced with 2 x SDA9253. Each SD9253 is a complete field store, its ports are
12 bit wide, and its memory capacity is triple that of the SD9251 (2.6Mbits). The operation of both type
of devices are the same, for purposes the only difference is the width of the ports. Therefore, we shall
only discuss the SD9253.
SDA9251 has been replaced with 2 x SDA9253. Each SD9253 is a complete field store, its ports are
12 bit wide, and its memory capacity is triple that of the SD9251 (2.6Mbits). The operation of both type
of devices are the same, for purposes the only difference is the width of the ports. Therefore, we shall
only discuss the SD9253.
The three ports are called A, B and C, port C is the input from the picture processor. Port B is the
back channel and port A is the output to the field mixer. These ports can be enabled or disable
depending whether the device is being written to or its being read with the exception of port 'A' which
is always enabled.
back channel and port A is the output to the field mixer. These ports can be enabled or disable
depending whether the device is being written to or its being read with the exception of port 'A' which
is always enabled.
The table below shows the function of various signals supplied to these Dynamic Sequential Access
Memories. You will notice that all signals are inputs, apart from ports A and B.
Memories. You will notice that all signals are inputs, apart from ports A and B.
Name
In/Out
Active
Level
Level
D
ESCRIPTION
SQA 0~11
O
Port A
SCA
I
Port A – Serial Clock
RA
I
L
Read Transfer Control (Latch A to Register A)
OEA
I
L
Port A – Output Enable
SQB 0~11
O
Port B
SCB
I
Port B – Serial Clock
RB
I
L
Read Transfer Control (Latch B to Register B)
OEB
I
L
Port B – Output Enable
SDC 0~11
I
Port C
WT
I
L
Write Transfer Control (Latch C to Register C)
SAR
I
Serial Row Address
SAC
I
Serial Column Address
SCAD
I
Serial Address Clock
RE
I
L
RAM Enable
Note
All timing signals are derived from the Memory Control IC, although some are routed via the
Field Mixer IC.
Field Mixer IC.
Wide Screen, Colour Television CW100 Chassis
Sharp Electronics (UK) Ltd
Technical Support
February 99
Page 18
F
IELD
M
IXER
The function of the field mixer is to produce an output signal which would have two fields for ever one
50Hz field, therefore doubling the field frequency to 100Hz.
50Hz field, therefore doubling the field frequency to 100Hz.
Note:
50Hz system
Interlace Scanning, two fields = one frame,
Field frequency = 50 Hz, therefore, frame frequency = 25
Each field consists of 312.5 lines
Field frequency = 50 Hz, therefore, frame frequency = 25
Each field consists of 312.5 lines
100Hz system
Frame frequency remains at 25Hz
Four Fields per frame, therefore field frequency = 100Hz
Each field consists of 312.5 lines, but since there are twice the number of fields within the
same frame rate the line frequency doubles.
Four Fields per frame, therefore field frequency = 100Hz
Each field consists of 312.5 lines, but since there are twice the number of fields within the
same frame rate the line frequency doubles.
The Field Mixer will use a motion predictor circuit to calculate movement between field A and Field B,
this data is then inserted between each Field A and Field B as field B-A, as shown in Figure 1
this data is then inserted between each Field A and Field B as field B-A, as shown in Figure 1
Figure 2 Field Frequency
To ensure that the picture remains synchronised the Memory Control IC will produce a 100Hz vertical
sync plus (VS2) from the VS sync pulse and a 31.25kHz horizontal sync pulse (BLN2) from BLN
sync plus (VS2) from the VS sync pulse and a 31.25kHz horizontal sync pulse (BLN2) from BLN
The Field Mixer has addition function, which allows you to enlarge the picture, whether the image is
moving or still.
moving or still.
D
ISPLAY
P
ROCESSOR
This is a triple 9-bit digital to analogue converter the designed of this 'IC' allows for any digital
component video signal format from 4:1:1 to 4:4:4 to be converted to analogue component video
(Y:U:V), our input source is 4:1:1 format.
component video signal format from 4:1:1 to 4:4:4 to be converted to analogue component video
(Y:U:V), our input source is 4:1:1 format.
From the Display Processor the Y:U:V is fed to the Colour Difference Amplifier (CDA) where if is
converted into an RGB signal before being past to the RGB output stage on the CRT base.
converted into an RGB signal before being past to the RGB output stage on the CRT base.
The RGB signal from the Megatext chip, which contains the On Screen Display data is add in at the
CDA chip.
CDA chip.
Field A
Field B
Field B
Field A
Frame
(25Hz)
(25Hz)
Field A
Field A-B
Field B
Field A
Field B-A
Field B
50Hz system
100Hz system
Wide Screen, Colour Television CW100 Chassis
Sharp Electronics (UK) Ltd
Technical Support
February 99
Page 19
Self Assessment Question
During 100Hz scan, what is the frame frequency?
How many fields per frame (100Hz)?
Why is the line frequency double?
What is the difference in number of pixels per line (picture area) between NTSC & PAL?
Wide Screen, Colour Television CW100 Chassis
Sharp Electronics (UK) Ltd
Technical Support
February 99
Page 20
Sync Signal Processor
60 Min Study Period
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