Sharp 32JF-77 (serv.man13) Service Manual ▷ View online
72
32JF-77H
SDA9380 (IC6006)
Pin Configuration
1
2
3
4
5
6
7
8
9
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SDA 9380
64 63 62 61 60 59 58 57 56 55 54 53
51
52
50 49
17 18 19 20 21 22 23 24 25 26 27 28
30
29
31 32
X2
X1
CLEXT
TEST
VSS
(D
)
CLKI
FB
L
2
FB
L
1
V
D
D(
D)
SVM
B/V 1
SSD
R2
G2
B2
VD
D
(M
C
)
RO
UT
GOU
T
BO
U
T
SC
P
VSS
(M
C
)
SUBST
RESN
SCL
SDA
VDD(D)
VSS(D)
HD
H35K
H38K
PWM
FH
1
_
2
G/U 1
R/Y 1
R/Y 1
SWI
T
C
H
V/B 0
U/G 0
U/G 0
Y/R 0
VSS(A4)
VDD(A4)
DCI
VREFC
VREFN
VBLO
VBLO
VREFH
PROTON
IBEAM
BSOIN
VSYNC
H
SYN
C
VD
D
(A1)
VS
S(
A1
)
VD
D
(A2)
VS
S(
A2
)
E/
W
H
SAF
E
HP
R
O
T
VP
R
O
T
VS
S(
A3
)
VD
D
(A3)
VD
-
VD
+
D/
A
Φ
=2
73
32JF-77H
SDA9380 (IC6006)
Pin Description
Pin No.
Name
Type
Description
1
CLKI
I/TTL
Input for external line locked clock *)
2
X2
Q
Reference oscillator output, Crystal
3
X1
I
Reference oscillator input, Crystal
4
CLEXT
I/TTL
Switching between internal (L) and external clock (H) *)
5
TEST
I/TTL
Switching between normal operation (TEST=L) and test mode
(TEST=H: pins 4, 12, 13, 14, 15, 17, 49, 50, 63, 64 are additio-
nal test pins)
(TEST=H: pins 4, 12, 13, 14, 15, 17, 49, 50, 63, 64 are additio-
nal test pins)
6
SUBST
S
Substrate pin, has to be connected to ground whenever a
power supply or signal is applied
power supply or signal is applied
7
RESN
I/TTL
Reset input, active Low
8
SCL
I
I²C Bus clock
9
SDA
IQ
I²C Bus data
10
VDD(D)
S
Digital supply
11
VSS(D)
S
Digital ground
12
HD
Q
Control signal output for H driver stage (open drain)
13
H35K
Q/TTL
Goes High when frequency of HSYNC is about 35kHz or more
14
H38K
Q/TTL
Goes High when frequency of HSYNC is about 38kHz
15
PWM
Q/TTL
Pulse width modulated control signal output
16
VSYNC
I/TTL
V-sync input
17
FH1_2
I/TTL
Switching between 1f
H
mode (L) and 2f
H
mode (H)
18
HSYNC
I
HSYNC input (CLEXT=H: TTL; CLEXT=L: analog) *)
19
VDD(A1)
S
Analog supply
20
VSS(A1)
S
Analog ground
21
Φ
2
I
Line flyback for H-delay compensation
22
VDD(A2)
S
Analog supply
23
VSS(A2)
S
Analog ground
24
E/W
Q
Control signal output for East-West raster correction
25
D/A
Q
Output of an I²C Bus controlled DC voltage
26
VD+
Q
Control signal output for DC coupled V-output stage
27
VD-
Q
Like VD+
28
VDD(A3)
S
Analog supply
29
VSS(A3)
S
Analog ground
30
VPROT
I
Watching external V-output stage (input is the V-saw-tooth from
feedback resistor)
feedback resistor)
31
HPROT
I
Watching EHT (input is e.g. H-flyback)
32
HSAFE
I
Watching B+ when frequency of HD has to be decreased
33
BSOIN
I
Input for starting Black Switch-Off
34
IBEAM
I
Input for a beam current dependent signal for stabilization of
width, height and H-phase
width, height and H-phase
35
PROTON
Q/TTL
Protection on (goes High after response of H- or V-protection)
74
32JF-77H
*) The external clock mode can not be used with 18.75, 33.75kHz, 35kHz and 38kHz line frequency.
36
VREFH
IQ
Reference voltage
37
VBLO
Q/TTL
Vertical blanking output
38
VREFN
IQ
Ground for VREFH
39
VREFC
I
Reference current input
40
DCI
I
Dark current input for cut off and white level control
41
VDD(A4)
S
Analog supply
42
Y/R 0
I
Luminance or R input
43
U/G 0
I
U signal or G input
44
V/B 0
I
V signal or B input
45
VSS(A4)
S
Analog ground
46
R/Y 1
I
First R or Y input for insertion
47
G/U 1
I
First G or U input for insertion
48
B/V 1
I
First B or V input for insertion
49
FBL1
I
Fast blanking input for RGB1
50
FBL2
I
Fast blanking input for RGB2
51
R2
I
Second R input for insertion
52
G2
I
Second G input for insertion
53
B2
I
Second B input for insertion
54
VDD(MC)
S
Analog supply for RGB output stage
55
ROUT
Q
R output
56
GOUT
Q
G output
57
BOUT
Q
B output
58
SCP
Q
Blanking signal with H- and color burst component
(V-component selectable by I²C Bus)
(V-component selectable by I²C Bus)
59
VSS(MC)
S
Analog ground for RGB output stage
60
SVM
Q
Luminance output for scan velocity modulation circuit
61
VDD(D)
S
Digital supply
62
VSS(D)
S
Digital ground
63
SSD
I/TTL
Disables softstart
64
SWITCH
Q/TTL
Output of an I²C Bus controlled switch (register 00, bit SW)
Pin No.
Name
Type
Description
SDA9380 (IC6006)
Pin Description
75
32JF-77H
76
79
2
13
6
19
7
71
8
74
32
31
30
22
21
16
15
10
9
38
48
47
46
37
41
40
39
52
53
54
55
56
57
58
CV
B
S
/C
YU
V
YU
V
YU
V
YU
V
YU
V
YU
V
4:
4
:4
4:
2:
2
4:
2:
2
4
:4
:4
a
d
ap
ti
ve
P
eak
in
g
I²C
in
te
rf
ace
ad
r/
td
i
s
c
l
sd
a
V
DAC
U
D
A
C
Y
DAC
O
FFS
ET
GA
IN
GA
IN
O
FFS
ET
O
FFS
ET
GA
IN
ADC1
63
GA
IN
ADC2
GA
IN
Sou
rc
e
S
e
lect
Sou
rc
e
S
e
lect
ADCR
GA
IN
ADCG
GA
IN
ADCB
GA
IN
ADCF
GA
IN
No
tc
h
,
D
esk
ew
,
de
la
y
Sy
n
c
Co
lo
r
D
e
c
ode
r
de
la
y
co
nt
ro
l
(P
AL
/SEC
AM)
1H
d
el
ay
pr
e
pr
oc
e
s
s
ing
pr
e
pr
oc
e
s
s
ing
pr
e
pr
oc
e
s
s
ing
A
n
ti
a
lia
s
,
D
e
s
kew
te
s
t-c
o
n
tr
o
ll
e
r,
m
e
m
o
ry
b
is
t
tc
lk
tm
s
xt
al
o
s
c
ill
a
to
r
x
out
xi
n
di
vi
d
e
r
IT
U
6
5
6
D
eco
de
r
65
6hi
o/
cl
kf
2
0
656
vi
o/
bl
an
k
RGB
YUV
or
b
ypa
ss
co
nt
ra
st
b
ri
ght
ne
s
s
sat
u
rat
io
n
τ
Of
fs
e
t,
Ga
in
s
o
ft-
mi
x
c
h
a
nne
l
mu
x
do
w
n
s
a
m
p
lin
g
2
4:
4:
4
4:
2:
2
H-
p
res
cal
er
no
is
e
me
a
s
u
re
me
n
t
pa
tt
e
rn
ge
ne
ra
to
r
fr
a
m
e
ge
ne
ra
to
r
IT
U
6
5
6
/
DS
6
5
6
En
c
o
d
e
r
de
la
y
ad
ju
st
8:
8:
8
te
mp
o
ra
l
noi
s
e
re
d
u
c
ti
o
n
NR
mo
ti
o
n
d
e
tect
io
n
e
D
RAM
me
mo
ry
co
n
tr
o
ll
er
H-
p
o
st
scal
er
V
H
av
out
au
ou
t
ay
ou
t
h
out
vo
ut
cl
k
out
v5
0/
bl
an
k
h5
0/
ir
q
vi
n/
in
tr
cv
bs
o3
cv
bs
o
2
cv
bs
o1
cv
b
s
1
cv
b
s
2
cv
b
s
3
cv
b
s
4
cv
b
s
5
cv
b
s
6
cv
b
s
7
ri
n
1
gi
n1
bi
n1
ri
n
2
gi
n2
bi
n2
fb
l2
fb
l1
65
6cl
k
65
6i
o0
65
6i
o1
65
6i
o2
65
6i
o3
65
6i
o4
65
6i
o5
65
6i
o6
65
6i
o7
CL
A
M
P
CL
A
M
P
c
lam
pi
n
g
s
ig
n
a
ls
to
A
DCs
AG
C
g
ene
ra
to
r
OP
T
IM
U
S
VSP 9
4
x
7
B
(p
inni
ng
c
o
rr
e
s
pon
ds
t
o
Q
F
P
-80
pac
k
a
ge)
C
VBS
/Y
YU
V
Y
U
V
F
α
ma
in
in
se
rt
da
ta b
uffe
r
da
ta b
uffe
r
re
s
e
t
di
v
id
e
r
line
-l
oc
ke
d
cl
o
c
ks
(3
6,
7
2
M
H
z
)
fr
e
e
-r
u
nni
ng
cl
oc
ks
(2
0.
25,
4
0
.5
M
H
z
)
c
lam
pe
d,
f
ilt
er
d
s
y
n
c
s
ig
n
a
l
fr
o
m
m
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ste
r
d
e
co
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r
Ou
tp
u
t
Da
ta
Co
n
tr
o
ll
e
r
Ou
tp
u
t S
y
n
c
Co
n
tr
o
ll
e
r
648
M
H
z
DT
O
LL
-P
L
L
6
48
M
H
z
c
lk
21
6
M
H
z
c
lk
lin
e
-l
o
cke
d
YU
V-
>
RG
B
o
r
by
pa
s
s
Pi
x
e
l-
mi
x
e
r
cu
rt
ai
n
ge
ne
ra
to
r
CT
I
LT
I
DC
I
a
d
ap
ti
ve
P
eak
in
g
CT
I
LT
I
No
tc
h
,
D
esk
ew
,
de
la
y
Sy
n
c
Co
lo
r
D
e
c
ode
r
de
la
y
co
n
tr
o
l
(P
AL
/SEC
AM)
1H
d
el
ay
V
H
c
lam
pi
n
g
s
ig
n
a
ls
to
A
DCs
AG
C
gen
er
a
tor
H-
p
o
st
scal
er
V-
p
o
s
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er
le
tt
e
rb
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o
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e
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ra
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mp
o
ra
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NR
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e
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e
me
mo
ri
e
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ic
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C
800
co
n
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Co
m
b
Fi
lt
e
r
4
H
d
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In
p
u
t
M
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IT
U
6
5
6
me
mo
ry
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tp
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ra
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pa
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pa
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p
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V-
p
re
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le
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lin
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me
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ob
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fi
lm
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P
-
E
n
gi
ne
m
o
ti
o
n
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ti
ve
u
p
c
onv
e
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ion
da
ta
sl
ic
e
r
no
is
e
me
a
s
u
re
me
n
t
pi
c
tur
e
no
is
e
m
easu
re
me
n
t
H-
p
res
cal
er
mo
s
a
ic
mo
d
e
ma
s
te
r
ou
tp
ut
sl
a
v
e
ou
tp
ut
62
61
24
14
20
18
69
70
27
23
17
to
6
5
6
io
gr
e
y
s
h
a
de
d
bl
oc
k
s
n
o
t
a
v
a
ila
b
le
in
V
S
P
94x
5B
80
78
79
77
75
76
i6
56i
cl
k
1
2
3
i6
5
6
i0
i6
5
6
i1
i6
5
6
i2
i6
5
6
i3
i6
5
6
i4
i6
5
6
i5
i6
56i
6
i6
56i
7
to
656
dec
od
er
940
x
B
,
94
3xB
onl
y
941
xB
,
94
4xB
onl
y
VSP9407 (IC6007)
Block Diagram
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