Sharp 28KF-84H (serv.man18) Service Manual ▷ View online
61
28KF-84H
*) The external clock mode can not be used with 18.75, 33.75kHz, 35kHz and 38kHz line frequency.
36
VREFH
IQ
Reference voltage
37
VBLO
Q/TTL
Vertical blanking output
38
VREFN
IQ
Ground for VREFH
39
VREFC
I
Reference current input
40
DCI
I
Dark current input for cut off and white level control
41
VDD(A4)
S
Analog supply
42
Y/R 0
I
Luminance or R input
43
U/G 0
I
U signal or G input
44
V/B 0
I
V signal or B input
45
VSS(A4)
S
Analog ground
46
R/Y 1
I
First R or Y input for insertion
47
G/U 1
I
First G or U input for insertion
48
B/V 1
I
First B or V input for insertion
49
FBL1
I
Fast blanking input for RGB1
50
FBL2
I
Fast blanking input for RGB2
51
R2
I
Second R input for insertion
52
G2
I
Second G input for insertion
53
B2
I
Second B input for insertion
54
VDD(MC)
S
Analog supply for RGB output stage
55
ROUT
Q
R output
56
GOUT
Q
G output
57
BOUT
Q
B output
58
SCP
Q
Blanking signal with H- and color burst component
(V-component selectable by I²C Bus)
(V-component selectable by I²C Bus)
59
VSS(MC)
S
Analog ground for RGB output stage
60
SVM
Q
Luminance output for scan velocity modulation circuit
61
VDD(D)
S
Digital supply
62
VSS(D)
S
Digital ground
63
SSD
I/TTL
Disables softstart
64
SWITCH
Q/TTL
Output of an I²C Bus controlled switch (register 00, bit SW)
Pin No.
Name
Type
Description
SDA9380 (IC6006)
Pin Description
62
28KF-84H
PRIMUS
VSP 9402A
VSP 9432A
VSP 9432A
1
2
3
4
5
6
7
8
9
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
11
12
13
14
15
16
17
18
19
20
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
vdddacy
ayout
auo
ut
a
v
out
vssdacy
vssd2
vddd2
sda
tms
vssp2
vddp2
scl
v
hout
h50
adr/tdi
v50
(reserved)
bin1
vddargb
vssargb
vdd33rgb
rin2
gin2
bin2
vddac1
vssac1
cvbs1
cvbs2
cvbs3
cvbs4
vdd33c
vss33c
vss33rgb
cvbso1
vdda
c
2
vssac2
vd
dd1
vss
d
1
vdd
apll
xou
t
xin
vd
dp1
vss
p
1
vdd
dacv
vss
d
a
cv
vddd
acu
vssdacu
gin1
ri
n
1
fb
l2
fb
l1
v
s
s
af
bl
vd
dafbl
vssd4
vdd
d4
v
ssd3
vdd
d3
clkou
t
v
ssp3
vdd
p3
vou
t
reset
cvbs5
cvbs6
cvbs7
cvbso2
cvbso3
656clk
656io7
656io6
656io5
656io5
656
io4
656
io3
656
io1
65
6io0
65
6hin/c
lkf2
0
656vin/blank
tcl
k
65
6io2
SDA9380 (IC6006)
Pin Assignments
VSP9402A (IC6007)
Pin Assignments
1
2
3
4
5
6
7
8
9
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SDA 9380
64 63 62 61 60 59 58 57 56 55 54 53
51
52
50 49
17 18 19 20 21 22 23 24 25 26 27 28
30
29
31 32
X2
X1
CLEXT
TEST
VSS
(D
)
CLKI
FB
L
2
FB
L
1
V
D
D(
D)
SVM
B/V 1
SSD
R2
G2
B2
VD
D
(M
C
)
RO
UT
GOU
T
BO
U
T
SC
P
VSS
(M
C
)
SUBST
RESN
SCL
SDA
VDD(D)
VSS(D)
HD
H35K
H38K
PWM
FH
1
_
2
G/U 1
R/Y 1
SWI
T
C
H
V/B 0
U/G 0
U/G 0
Y/R 0
VSS(A4)
VDD(A4)
DCI
VREFC
VREFN
VBLO
VREFH
PROTON
IBEAM
BSOIN
VSYNC
H
SYN
C
VD
D
(A1)
VS
S(
A1
)
VD
D
(A2)
VS
S(
A2
)
E/
W
H
SAF
E
HP
R
O
T
VP
R
O
T
VS
S(
A3
)
VD
D
(A3)
VD
-
VD
+
D/
A
Φ
=
2
63
28KF-84H
VSP9402A (IC6007)
Block Diagram
13
6
I²C
interface
(5
6
)
19
adr/tdi
s
c
l
s
da
V
DA
C
(5
4
)
U
DA
C
(5
3
)
Y
DA
C
(5
2
)
O
FFS
E
T
GA
IN
76
2
79
GA
IN
O
FFS
E
T
O
FFS
E
T
GA
IN
AD
C1
(2
)
52
63
62
61
53
54
58
55
56
57
39
40
41
48
37
46
47
GA
IN
AD
C2
(3
)
GA
IN
S
ource
S
e
lect
(1
)
S
ource
S
e
lect
(1
6
)
38
AD
CR
(1
2
)
GA
IN
AD
CG
(1
3
)
GA
IN
AD
CB
(1
4
)
GA
IN
A
DCF
(1
5
)
GA
IN
Notch
Deskew
(4
)
Sy
n
c
(6
)
Color
Decoder
(5
)
delay
control
(P
AL
/S
E
C
AM
)
(7
)
1H delay
18
20
Ant
ial
ias,
Deskew
(1
7
)
Ant
ial
ias,
Deskew
(1
8
)
Ant
ial
ias,
Deskew
(1
9
)
Ant
ial
ias,
Deskew
(2
0
)
test-
controller
,
memo
ry
bist
(5
5
)
71
7
tc
lk
tms
69
70
xtal
o
s
cillator
(9
)
x
out
xin
divider
32
31
30
15
22
21
16
10
9
74
8
ITU
656
D
ecoder
(4
1
)
656hi
n/
cl
kf
2
0
656vin/
blank
CLK
F20
RG
B
YU
V
or
bypass
(2
5
)
τ
(2
7
)
Y
brightne
s
s
c
ontra
s
t
(2
6
)
U,
V
s
a
tura
ti
on
O
ffset,
Gain
(2
9
)
(3
0
)
soft-mix
ch
a
n
nel
mux
(3
1
)
do
w
n
sampling
2
4:4:4
4:2:2
(2
8
)
H-
pr
escaler
(3
4
)
noise
measure
men
t
(3
2
)
clampin
g
cor
rection
(2
1
)
clampin
g
cor
rection
(2
2
)
clampin
g
cor
rection
(2
3
)
DC
T
I
(4
6
)
P
eaking
(4
5
)
C
o
ar
se
Delay
4:4:4
(4
9
)
ITU656
E
n
coder
(5
1
)
8
8:8:8
(5
0
)
Fin
e
de
la
y
Y noise
re
duction
(3
8
)
UV
moti
o
n
detection
(3
6
)
Y motion
detection
(3
5
)
UV
noise
re
duction
(3
7
)
eDR
AM
memory
controller
(3
9
)
14
23
17
27
Pix
e
lmixer
(44)
H-
pos
ts
c
a
le
r
(4
2
)
Panorama
ge
ne
ra
tor
(4
3
)
V
H
avout
au
out
ayout
ho
u
t
vout
cl
ko
u
t
v5
0
h50
v
cv
bs
o3
cvb
s
o
2
cvb
so
1
cv
bs
1
cv
bs
2
cv
bs
3
cv
bs
4
cv
bs
5
cv
bs
6
cv
bs
7
rin1
gi
n1
bi
n1
rin2
gi
n2
bi
n2
fbl2
fbl1
656c
lk
656i
o0
656i
o1
656i
o2
656i
o3
656i
o4
656i
o5
656i
o6
656i
o7
CLAMP
CLAMP
c
lam
pi
ng
s
ig
n
a
ls
to
A
DCs
AG
C
g
ener
at
o
r
Y
d
e
la
y
(8
)
PRIMUS
(A32
)
VSP9402A
VSP9432A
CLK
B3
6
Y
U,
V
C
VBS/
Y
C
YC
SEL
Y
U,
V
Y
U
V
F
α
ma
in
in
s
e
rt
CL
KF2
P
A
D
Y
del
a
y
UV
del
a
y
UV
in
Y
in
data
bu
ffe
r
data
bu
ffe
r
24
res
et
line locked or
free-r
unnin
g
divider
line-loc
k
e
d
cl
o
c
k
s
(3
6
, 7
2
M
H
z
)
free-running
cl
o
c
ks
(2
0.
2
5
,
40.
5
MH
z)
c
lampe
d,
f
ilt
er
d
sy
n
c
s
ig
na
l
K
c
Ky
de
t_
bl
oc
k
.v
s
d 1
/.
1
0.
20
00
D
.W
e
n
del
O
u
tput
Dat
a
Contr
o
lle
r
(5
5
)
re
a
d
con
tr
o
l
H/V-
ac
quisition
(3
3
)
In
p
u
t
Sync
Ou
tp
u
t
Sy
n
c
B
a
ck
gr
ou
nd
gen
er
a
tor
(5
7
)
O
u
tput
Sy
n
c
C
ont
ro
ller
(4
0
)
64
8 MH
z
DT
O
(1
0
)
LL-
P
L
L
(1
1
)
64
8
M
H
z
c
lk
2
16
M
H
z
cl
k
line
-l
o
c
ked
BL
A
N
K
BL
ANE
N
BL
ANK
FB
64
28KF-84H
VSP9402A (IC6007)
Pin Description
pin 9402/32 9412/42 I/O
9402/32
9412/42
remark
52
cvbs1
I
CVBS input
analog input
53
cvbs2
I
CVBS input
analog input
54
cvbs3
I
CVBS input
analog input
55
cvbs4
I
CVBS input or Y1
analog input
56
cvbs5
I
CVBS input or C1
analog input
57
cvbs6
I
CVBS input or Y2
analog input
58
cvbs7
I
CVBS input or C2
analog input
63
cvbso1
O
CVBS output 1
CVBS output 2
CVBS output 2
analog output
62
cvbso2
O
analog output
61
cvbso3
O
CVBS output 3
analog output
70
xin
I
Crystal connection 1
69
xout
O
Crystal connection 2
23
vout
O
vertical output
single or double
scan, dependent
on version
17
hout
O
horizontal output
3
vssdacy
i656i7
S/I
DAC (Y)
656 input
(MSB)
2
ayout
i656i6
O/I
Y output
656 input
1
vdddacy
i656i5
S/I
DAC (Y)
656 input
80
vssdacu
i656i4
S/I
DAC (U)
656 input
79
auout
i656i3
O/I
U output
656 input
78
vdddacu
i656i2
S/I
DAC (U)
656 input
77
vssdacv
i656i1
S/I
DAC (V)
656 input
76
avout
i656i0
O/I
V output
656 input
(LSB)
75
vdddacv
i656iclk
S/I
DAC (V)
656 input
clock
27 MHz nom.
39
rin1
I
R or V in1
analog input
40
gin1
I
G or Y in1
analog input
41
bin1
I
B of U in1
analog input
37
fbl1
I
Fast Blank input 1 (H1)
analog input
46
rin2
I
R or V in2
analog input
47
gin2
I
G or Y in2
analog input
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