Sharp 28KF-84H (serv.man18) Service Manual ▷ View online
57
28KF-84H
Fig.1 Block diagram.
handbook, full pagewidth
DIFFERENTIAL
STAGE
MIRROR
MIRROR
CURRENT
SOURCE
MIRROR
MIRROR
TDA6111Q
7 V
supply voltage
input HIGH
feedback
output
6
Vbias
FOLLOWERS
C par
9
non-inverting
input
inverting
input
3
1
4
2
ground
(substrate)
supply voltage
input LOW
7
8
5
cathode
transient
output
transient
output
cathode
DC output
DC output
black current
measurement
output
measurement
output
MGA058
SYMBOL
PIN
DESCRIPTION
V
ip
1
non-inverting voltage input
V
DDL
2
supply voltage LOW
V
in
3
inverting voltage input
GND
4
ground, substrate
I
om
5
black current measurement
output
output
V
DDH
6
supply voltage HIGH
V
cn
7
cathode transient voltage output
V
oc
8
cathode DC voltage output
V
fb
9
feedback voltage output
Fig.2 Pin configuration.
ndbook, halfpage
MGA057
1
2
3
4
5
6
7
8
9
DDL
V
GND
TDA6111Q
ip
V
in
V
om
I
oc
V
cn
V
fb
V
DDH
V
TDA6111Q (IC850, IC851, IC852)
Block Diagram
Pin Description
Pin Assignments
58
28KF-84H
SDA5550 (IC6001)
Block Diagram
Pin Assignments
Memory
Extension Unit
06
Core
Interrupt
Controller
Counter 1
Counter 0
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Display logic
Display
Regs
3RUW/RJLF
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A
D
C
X
4
P
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o
4]
A
[0 t
o
15]
D[
0
t
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7
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AL
E
PS
EN
RD
WR
A[
1
6
t
o
A2
0
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V
B
S
P0
.0
.0
P0
.1
.1
P0
.2
.2
P0
.3
.3
P0
.4
.4
P0
.5
.5
P0
.6
.6
P0
.7
.7
VDD 2
.5
VS
S
S
VDD 3
.3
C
VBS
V
DDA 2
.5
VS
SA
SA
P2
.0
.0
P2
.1
.1
P2
.2
.2
P2
.3
.3
H
S
/ S
S
C
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.1
P3.2
P3.3
P3.4
P3.5
VS
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1
P1.0
V
DD 3
.3
VS
S
S
V
DD 2
.5
BL
AN
K
AN
K
/
C
O
O
R
B
G
R
V
DDA 2
.5
VS
SA
SA
XT
A
A
L
1
XT
A
A
L
2
P4.3
P4.2
VDD 3.3
VSS
P3.7
P3.6
RST
D3
XR
O
O
M
P1
.7
.7
A7
A1
3
3
A1
2
2
A1
4
4
A1
5
5
A1
7
7
A1
6
6
A1
8
8
A1
9
9
A8
A6
A9
A5
A11
A4
PSEN
A3
A10
VSS
VDD 3.3
A2
A1
D7
A0
D6
D0
D5
D1
D4
D2
EN
E
E
ST
O
O
P
OC
F
RD
WR
FL
_R
S
_R
S
T
FL_CE
FL
_P
G
_P
G
M
ALE
EX
T
T
IF
TV
TE
X
TE
X
T
P
R
O
SD
A
A
5
5
XX
P-
M
M
Q
F
P
-1
0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
3
1
32
33
3
4
35
36
3
7
38
39
40
41
42
43
4
4
45
46
47
4
8
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
10
0
0
9
9
80
59
28KF-84H
SDA9380 (IC6006)
Block Diagram
VSYNC
HSYNC
HSYNC
CONTROL
PLL
CLL
HPROT
VBLO
X1
X2
X2
VREFC
SCL
SDA
TEST
CLKI
PROTECTION
START UP
H-OUT
V-OUT
EW-OUT
AVERAGE
BEAM LIMITER
HD
VD+
VD-
VD-
E/W
φ2
φ2
φ2
φ2
VPROT
SSD
IBEAM
H35K
RESN
SWITCH
D/A
BSOIN
H38K
VREFH
VREFN
HSAFE
PW/PH-CORR
CLAMP
CLAMP
CLAMP
BLACK
STRETCH
SATURATION
CONTROL
CUT OFF +
WHITE POINT
OUTPUT
BUFFER
RGB
MATRIX
BRIGHTNESS
CONTROL
DELAY
RGB/YUV 1
RGB 2
3
3
3
3
FBL 2
FBL 1
FBL 1
DCI
ROUT
GOUT
BOUT
GOUT
BOUT
YUV/RGB 0
3
3
3
3
Y
SVM
CLEXT
VDD(A1..4)
VSS(A1..4)
VDD(D1..2)
VSS(D1..2)
VDD(MC)
VSS(MC)
SUBST
PWM
PWM
MATRIX
MATRIX
MEASURE
PULSES
3
2
3
3
3
YUV
YUV
Y
UV
UV
3
3
3
PEAK DRIVE
LIMITER
BLUE STRETCH
CONTRAST
CONTROL
SWITCH
MATRIX
3
YUV
FH1_2
SCP
I²C
PROTON
60
28KF-84H
SDA9380 (IC6006)
Pin Description
Pin No.
Name
Type
Description
1
CLKI
I/TTL
Input for external line locked clock *)
2
X2
Q
Reference oscillator output, Crystal
3
X1
I
Reference oscillator input, Crystal
4
CLEXT
I/TTL
Switching between internal (L) and external clock (H) *)
5
TEST
I/TTL
Switching between normal operation (TEST=L) and test mode
(TEST=H: pins 4, 12, 13, 14, 15, 17, 49, 50, 63, 64 are additio-
nal test pins)
(TEST=H: pins 4, 12, 13, 14, 15, 17, 49, 50, 63, 64 are additio-
nal test pins)
6
SUBST
S
Substrate pin, has to be connected to ground whenever a
power supply or signal is applied
power supply or signal is applied
7
RESN
I/TTL
Reset input, active Low
8
SCL
I
I²C Bus clock
9
SDA
IQ
I²C Bus data
10
VDD(D)
S
Digital supply
11
VSS(D)
S
Digital ground
12
HD
Q
Control signal output for H driver stage (open drain)
13
H35K
Q/TTL
Goes High when frequency of HSYNC is about 35kHz or more
14
H38K
Q/TTL
Goes High when frequency of HSYNC is about 38kHz
15
PWM
Q/TTL
Pulse width modulated control signal output
16
VSYNC
I/TTL
V-sync input
17
FH1_2
I/TTL
Switching between 1f
H
mode (L) and 2f
H
mode (H)
18
HSYNC
I
HSYNC input (CLEXT=H: TTL; CLEXT=L: analog) *)
19
VDD(A1)
S
Analog supply
20
VSS(A1)
S
Analog ground
21
Φ
2
I
Line flyback for H-delay compensation
22
VDD(A2)
S
Analog supply
23
VSS(A2)
S
Analog ground
24
E/W
Q
Control signal output for East-West raster correction
25
D/A
Q
Output of an I²C Bus controlled DC voltage
26
VD+
Q
Control signal output for DC coupled V-output stage
27
VD-
Q
Like VD+
28
VDD(A3)
S
Analog supply
29
VSS(A3)
S
Analog ground
30
VPROT
I
Watching external V-output stage (input is the V-saw-tooth from
feedback resistor)
feedback resistor)
31
HPROT
I
Watching EHT (input is e.g. H-flyback)
32
HSAFE
I
Watching B+ when frequency of HD has to be decreased
33
BSOIN
I
Input for starting Black Switch-Off
34
IBEAM
I
Input for a beam current dependent signal for stabilization of
width, height and H-phase
width, height and H-phase
35
PROTON
Q/TTL
Protection on (goes High after response of H- or V-protection)
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