Sharp XV-C2E (serv.man4) Service Manual ▷ View online
XV-C2E
32
2) Terminals
Terminal No.
Symbol
Remarks
43
XCLP2
44
XCLP1
45
RGB GAIN
46
R GAIN
47
B GAIN
48
GND
49
IREF
50
V
CC
4
51
GCADET B
52
GCADET G
53
GCADET R
54
SIG SEL
55
GND
56
SH4
57
SH3
58
SH2
61
SH1
62
PV
CC
63
SH IN
64
GND
Reference signal pulse input
terminal.
When it is set at LOW, the signal
level becomes reference level.
terminal.
When it is set at LOW, the signal
level becomes reference level.
Input level
HIGH
>
4V
LOW
<
1V
Clamp pulse input terminal.
When it is set at LOW, clamp
becomes effective.
When it is set at LOW, clamp
becomes effective.
Input level
HIGH
>
4V
LOW
<
1V
Variable gain amplifier control
terminal common for RGB signals.
terminal common for RGB signals.
Variable gain amplifier control
terminal common for R signal.
It is internally preset at 3.3V.
terminal common for R signal.
It is internally preset at 3.3V.
Variable gain amplifier control
terminal common for B signal.
It is internally preset at 3.3V.
terminal common for B signal.
It is internally preset at 3.3V.
GND terminal.
Terminal to set the current of
sample hold circuit.
sample hold circuit.
5V power supply terminal.
B GCA circuit clamp detection
terminal.
terminal.
G GCA circuit clamp detection
terminal.
terminal.
R GCA circuit clamp detection
terminal.
terminal.
Switching terminal of signal to be
inputted in sample hold circuit.
When it is set at HIGH, the R and B
signals are selected and when it is
set at LOW, the G signal is se-
lected.
inputted in sample hold circuit.
When it is set at HIGH, the R and B
signals are selected and when it is
set at LOW, the G signal is se-
lected.
Input level
HIGH
>
4V
LOW
<
1V
GND terminal
Sample hold pulse input terminal.
Input level
HIGH
>
3.0V
LOW
<
1.0V
When it is set at HIGH, sampling
becomes effective and when it is
set at LOW, holding becomes
effective.
becomes effective and when it is
set at LOW, holding becomes
effective.
5V power supply terminal.
Terminal for input in sample/hold
circuit.
circuit.
GND terminal.
Terminal No.
Symbol
Remarks
B signal clamp detection terminal.
G signal clamp detection terminal.
R signal clamp detection terminal.
Black side voltage gain control
terminal common for RGB signals.
terminal common for RGB signals.
Black side voltage gain control
terminal for R signal.
It is internally preset at 3.3V.
terminal for R signal.
It is internally preset at 3.3V.
Black side voltage gain control
terminal for B signal.
It is internally preset at 3.3V.
terminal for B signal.
It is internally preset at 3.3V.
White side voltage gain control
terminal common for RGB signals.
terminal common for RGB signals.
White side voltage gain control
terminal for R signal.
It is internally preset at 3.3V.
terminal for R signal.
It is internally preset at 3.3V.
White side voltage gain control
terminal for B signal.
It is internally preset at 3.3V.
terminal for B signal.
It is internally preset at 3.3V.
White side voltage gain changing
point control common for RGB
signals.
point control common for RGB
signals.
White side voltage gain changing
point control for R signal.
It is internally preset at 3.3V.
point control for R signal.
It is internally preset at 3.3V.
White side voltage gain changing
point control for B signal.
It is internally preset at 3.3V.
point control for B signal.
It is internally preset at 3.3V.
Black side voltage gain changing
point control common for RGB
signals.
point control common for RGB
signals.
Black side voltage gain changing
point control for R signal.
It is internally preset at 3.3V.
point control for R signal.
It is internally preset at 3.3V.
Black side voltage gain changing
point control for B signal.
It is internally preset at 3.3V.
point control for B signal.
It is internally preset at 3.3V.
65
B CLAMP
66
G CLAMP
67
R CLAMP
68
RGB GAM
GAIN1
GAIN1
69
R GAM
GAIN1
GAIN1
70
B GAM
GAIN1
GAIN1
71
RGB GAM
GAIN2
GAIN2
72
R GAM
GAIN2
GAIN2
73
B GAM
GAIN2
GAIN2
74
RGB GAM
CTR2
CTR2
75
R GAM
CTR2
CTR2
76
B GAM
CTR2
CTR2
77
RGB GAM
CTR1
CTR1
78
R GAM
CTR1
CTR1
79
B GAM
CTR1
CTR1
XV-C2E
33
5. IC4302 (VHiCXD2443Q-1) Timing generator
1) Block Diagram
PHASE
COMPARATOR
COMPARATOR
FIELD & LINE
CONTROLLER
CONTROLLER
LOOP
FILTER
FILTER
PULSE ELIMINATOR
SERIAL I/F
V-SYNC SEPARATOR
H-SYNC DETECTOR
V-CONTROL COUNTER
H-SYNC DETECTOR
PHASE
COMPARATOR
COMPARATOR
PLL COUNTER2
DECODER
DECODER
&
V-TIMING PULSE
GENERATOR
DECODER
&
H-TIMING PULSE
GENERATOR
V-POSITION COUNTER
H-POSITION COUNTER
DOUBLE SCAN
CONVERTER
CONVERTER
PLL COUNTER
DECODER
RPD1
9
RPD2 87
RPD3 93
FPD1
6
FPD2 84
FPD3 96
HSYNC 13
VSYNC 14
VST 34
FLDO 21
VWA 30
VWB
2
PWM1
8
PWM2
86
PWM3
95
PEO1
7
PEO2
85
PEO3
94
HDR
100
HSTA
43
HCK1A
38
HCK2A
37
ENB
36
VCK
35
FRP
49
XFRP
50
PCG1
31
XCLP1
47
XCLP2
48
PCG2
46
SH1A
51
SH2A
52
SH3A
55
SH4A
56
SH5A
57
SH6A
58
SH7A
59
HSTB
42
HCK1B
41
HCK2B
39
SH1B
61
SH2B
62
SH3B
63
SH4B
64
SH5B
66
SH6B
67
SH7B
68
TC3
97
TC2
83
TC1
5
CKI3
92
CKI5
99
CKO3
91
HD
CKSL
98
SCTR 16
SCLK 17
SDAT 18
PRE 19
RPD4 76
FPD4 77
TC4
CLOCK2
TEST: 12, 20, 22, 23, 24, 25, 26, 27, 33, 60, 69
V
V
DD
:
3, 28, 53, 78
V
SS
:
4, 15, 29, 40, 54, 65, 79, 90
LOOP
FILTER
FILTER
DIRECT
CLEAR
CLEAR
82
WCK
72
RSTW
73
RSTR
71
XRGT
45
DWN
32
RGT
44
RCK
70
CKI4
75
CKO4
74
PEO4
80
CKI2
89
CKO2
88
16:9
MASTER CLOCK
CKI1
11
CKO1
10
4:3
PWM4
81
XCLR
1
XV-C2E
34
2) Functions of Terminals
Terminal
No.
Terminal
Name
I/O
Function
1
XCLR
I
System clear terminal (L: All clear)
2
VWB
O
V window pulse B output terminal
3
V
DD
–
Power
4
V
SS
–
GND
5
TC1
I/O
FPD1 output pulse regulation terminal (NTSC/PAL 4 : 3)
6
FPD1
O
Phase comparator 1 output terminal (NTSC/PAL 4 : 3)
7
PEO1
I/O
Loop filter integrator 1 output terminal (NTSC/PAL 4 : 3)
8
PWM1
O
Loop filter integrator 1 input terminal (NTSC/PAL 4 : 3)
9
RPD1
O
Phase comparator 1 output terminal (NTSC/PAL 4 : 3)
10
CKO1
I/O
Oscillation cell 1 output terminal (NTSC/PAL 4 : 3)
11
CKI1
I
Oscillation cell 1 input terminal (NTSC/PAL 4 : 3)
12
TEST2
I
Test terminal (Use it as open terminal.)
13
HSYNC
I
Horizontal sync signal input terminal (Polarity is set by serial data HPOL.)
14
VSYNC
I
Vertical sync signal input terminal (Polarity is set by serial data VPOL.)
15
V
SS
–
GND
16
SCTR
I
Chip selection input terminal (Serial transfer section)
17
SCLK
I
Serial clock input terminal (Serial transfer section)
18
SDAT
I
Serial data input terminal (Serial transfer section)
19
PRE
I
Presetting terminal (L: It is set at NTSC 4 : 3 mode)
20
TEST11
–
Test terminal (Use it as open terminal.)
21
FLDO
O
Field identify signal output terminal
22
TEST1
–
Test terminal (Use it as open terminal.)
23
TEST3
–
Test terminal (Use it as open terminal.)
24
TEST4
–
Test terminal (Use it as open terminal.)
25
TEST5
–
Test terminal (Use it as open terminal.)
26
TEST6
–
Test terminal (Use it as open terminal.)
27
TEST7
–
Test terminal (Connect it to GND.)
28
V
DD
–
Power
29
V
SS
–
GND
30
VWA
O
V window pulse A output terminal
31
PCG1
O
PCG1 pulse output terminal (Positive polarity)
32
DWN
O
Up/Down reverse identify signal output terminal (H: Down, L: Up)
33
TEST8
–
Test terminal (Use it as open terminal.)
34
VST
O
V start pulse output terminal (Positive polarity)
35
VCK
O
V clock pulse output terminal
36
ENB
O
ENB pulse output terminal (Negative polarity)
37
HCK2A
O
H clock 2A pulse output terminal
38
HCK1A
O
H clock 1A pulse output terminal
39
HCK2B
O
H clock 2B pulse output terminal
40
V
SS
–
GND
41
HCK1B
O
H clock 1B pulse output terminal
42
HSTB
O
H start B pulse output terminal (Positive polarity)
43
HSTA
O
H start A pulse output terminal (Positive polarity)
XV-C2E
35
Terminal
No.
Terminal
Name
I/O
Function
44
RGT
O
Right/Left reverse identify signal output terminal (H: Right, L:Left)
45
XRGT
O
Right/Left reverse identify signal output terminal (L: Left, H: Right)
46
PCG2
O
PCG2 pulse output terminal (Positive polarity)
47
XCLP1
O
Pedestal clamp pulse 1 output terminal (Negative polarity)
48
XCLP2
O
Pedestal clamp pulse 2 output terminal (Negative polarity)
49
FRP
O
AC drive reverse timing output terminal
50
XFRP
O
AC drive reverse timing output terminal (Reversion of FRP)
51
SH1A
O
Sample/hold pulse 1A output terminal (Positive polarity)
52
SH2A
O
Sample/hold pulse 2A output terminal (Positive polarity)
53
V
DD
–
Power
54
V
SS
–
GND
55
SH3A
O
Sample/hold pulse 3A output terminal (Positive polarity)
56
SH4A
O
Sample/hold pulse 4A output terminal (Positive polarity)
57
SH5A
O
Sample/hold pulse 5A output terminal (Positive polarity)
58
SH6A
O
Sample/hold pulse 6A output terminal (Positive polarity)
59
SH7A
O
Sample/hold pulse 7A output terminal (Positive polarity)
60
TEST9
–
Test terminal (Use it as open terminal.)
61
SH1B
O
Sample/hold pulse 1B output terminal (Positive polarity)
62
SH2B
O
Sample/hold pulse 2B output terminal (Positive polarity)
63
SH3B
O
Sample/hold pulse 3B output terminal (Positive polarity)
64
SH4B
O
Sample/hold pulse 4B output terminal (Positive polarity)
65
V
SS
–
GND
66
SH5B
O
Sample/hold pulse 5B output terminal (Positive polarity)
67
SH6B
O
Sample/hold pulse 6B output terminal (Positive polarity)
68
SH7B
O
Sample/hold pulse 7B output terminal (Positive polarity)
69
TEST10
–
Test terminal (Use it as open terminal.)
70
RCK
O
Read clock output terminal (for line buffer)
71
RSTR
O
Read reset output terminal (for line buffer, negative polarity)
72
WCK
O
Write clock output terminal (for line buffer)
73
RSTW
O
Write reset output terminal (for line buffer, negative polarity)
74
CKO4
I/O
Oscillation cell 4 output terminal (Line high-speed controller)
75
CKI4
I
Oscillation cell 4 input terminal (Line high-speed controller)
76
RPD4
O
Phase comparator 4 output terminal (Line high-speed controller)
77
FPD4
O
Phase comparator 4 output terminal (Line high-speed controller)
78
V
DD
–
Power
79
V
SS
–
GND
80
PEO4
I/O
Loop filter integrator 4 output terminal (Line high-speed controller)
81
PWM4
O
Loop filter integrator 4 input terminal (Line high-speed controller)
82
TC4
I/O
FPD 4 output pulse width regulation terminal (Line high-speed controller)
83
TC2
I/O
FPD 2 output pulse width regulation terminal (NTSC/PAL 16 : 9)
84
FPD2
O
Phase comparator 2 output terminal (NTSC/PAL 16 : 9)
85
PEO2
I/O
Loop filter integrator 2 output terminal (NTSC/PAL 16 : 9)
86
PWM2
O
Loop filter integrator 2 input terminal (NTSC/PAL 16 : 9)
87
RPD2
O
Phase comparator 2 output terminal (NTSC/PAL 16 : 9)
88
CKO2
I/O
Oscillation cell 2 output terminal (NTSC/PAL 16 : 9)
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