Sharp XV-C2E (serv.man4) Service Manual ▷ View online
XV-C2E
28
3) Functions of input/output terminals
13~16,
D
IN0
~
Data input
I
Write data input terminal.
21~24
D
IN7
Data is entered at the first leading edge after WCK input
cycle. The setup time and hold time (t
cycle. The setup time and hold time (t
DS
, t
DH
) are determined
at this time.
1~4,
D
OUT0
~
Data output
O
Read data output terminal.
9~12
D
OUT7
Access time is determined from the leading edge before RCK
input cycle and defined by t
input cycle and defined by t
AC
.
19
RSTW
Reset write input
I
Reset input terminal to initialize the write address pointer.
Reset signal is entered at the first leading edge after WCK
input cycle. The setup time and hold time (t
input cycle. The setup time and hold time (t
RS
, t
RH
) are de-
termined at this time.
6
RSTR
Reset read input
I
Reset input terminal to initialize read address pointer.
Reset signal is entered at the leading edge after WCK input
cycle. The setup time and hold time (t
cycle. The setup time and hold time (t
RS
, t
RH
) are determined
at this time.
20
WE
Write enable input
I
Write operation control input terminal.
When it is in disable mode (at high level), the internal write
operation is disabled and the write address pointer stops at
the current value, too.
operation is disabled and the write address pointer stops at
the current value, too.
5
RE
Read enable input
I
Read operation control input terminal.
When it is in disable mode (at high level), the internal read
operation is disabled and the read address pointer stops at
the current value, too.
In addition, the output becomes of high impedance.
operation is disabled and the read address pointer stops at
the current value, too.
In addition, the output becomes of high impedance.
17
WCK
Write clock input
I
Write clock input terminal.
When WE signal is enabled (at low level), the write opera-
tion is performed in synchronization with the write clock and
the write address pointer is incremented at the same time.
tion is performed in synchronization with the write clock and
the write address pointer is incremented at the same time.
8
RCK
Read clock input
I
Read clock input terminal.
When RE signal is enabled (at low level), the read operation
is performed in synchronization with the read clock and the
read address pointer is incremented at the same time.
is performed in synchronization with the read clock and the
read address pointer is incremented at the same time.
NO.
Symbol
Name
Terminal
I/O
Function
XV-C2E
29
3. IC4209 (VHiCXD1178Q-1) D/A converter
1) Block Diagram
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
47
48
36
37
27
43
44
45
46
38
39
28
33
30
31
40
41
29
42
34
33
32 VB
I
REF
V
REF
VG
BCK
BO
BO
DV
SS
DV
SS
AV
SS
AV
DD
AV
DD
DV
DD
DV
DD
AV
DD
AV
DD
GCK
RCK
GO
GO
RO
RO
+
–
CE
BLK
B7
B6
B5
B4
B3
B2
B1
G7
G6
G5
G4
G3
G2
G1
R7
R6
R5
R4
R3
R2
R1
(LSB)R0
(LSB)G0
(LSB)B0
DECODER
DECODER
DECODER
DECODER
DECODER
DECODER
LATCHES
LATCHES
LATCHES
2LSB'S
CURRENT
CELLS
2LSB'S
CURRENT
CELLS
2LSB'S
CURRENT
CELLS
6MSB'S
CURRENT
CELLS
6MSB'S
CURRENT
CELLS
6MSB'S
CURRENT
CELLS
CLOCK
GENERATOR
CLOCK
GENERATOR
CLOCK
GENERATOR
CURRENT CELLS
(FOR FULL SCALE)
BIAS VOLTAGE
GENERATOR
2) Remarks of Terminals and Input/Output Terminal Equivalent Circuit
Terminal No.
Symbol
Remarks
1~8
R0~R7
9~16
G0~G7
Digital input
17~24
B0~B7
25
BLK
Blanking terminal.
When it is set at "H", no signal is
outputted. (Output: 0V)
When it is set at "L", the signal is
outputted.
When it is set at "H", no signal is
outputted. (Output: 0V)
When it is set at "L", the signal is
outputted.
32
VE
Connect a 0.1uF or so capacitor.
27
RCK
Clock terminal.
28
GCK
All input terminals are compatible
29
BCK
with TTM-CMOS.
30, 31
DV
SS
Digital GND
33
AV
SS
Analog GND
26
CE
Chip enable terminal.
When it is set at "H", no signal is
outputted (Output: 0V) and the
power consumption is minimized.
When it is set at "H", no signal is
outputted (Output: 0V) and the
power consumption is minimized.
35
I
REF
Connect a "16R" resistor which
has 16 times larger value than the
output resistance value "R".
has 16 times larger value than the
output resistance value "R".
34
V
REF
Output full scale is set.
42
VG
Connect a 0.1uF or so capacitor.
43~46
AV
DD
Analog V
DD
37
RO
Current output terminal.
39
GO
Output can be taken out by con-
41
BO
necting a resistor.
36
RO
Reverse current output terminal.
38
GO
Normally, it is connected to the
40
BO
analog ground.
47, 48
DV
DD
Digital V
DD
Terminal No.
Symbol
Remarks
XV-C2E
30
4. IC4305 (VHiCXA1853Q-1) R.G.B driver
1) Block Diagram
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
N.C.
N.C.
SH2
SH3
SH4
GND
SIG SEL
GCA DETR
GCA DETG
GCA DETB
V
CC4
IREF
GND
B GAIN
R GAIN
RGB GAIN
XCLP1
XCLP2
GAM SEL
WHT LIM
BLK CENT
BLK LIM
VCOM OUT
SIG CENT CTR
VCOM CTR
PRG
GND
SID FRP
FRP
PRG CTR
SID CTR
SID CLP
R CLP
G CLP
B CLP
R SBRT
B SBRT
RGB SBRT
N.C.
GND
RGB MBRT
N.C.
N.C.
R MBRT
B MBRT
N.C.
GAM OUT
V
CC1
R IN
G IN
B IN
GND
SID OUT
V
CC2
R OUT
G OUT
B OUT
V
CC3
N.C.
N.C.
SH1
SH IN
GND
B CLAMP
G CLAMP
R CLAMP
RGB GAM GAIN1
RGB GAM GAIN2
RGB GAM CTR2
RGB GAM CTR1
R GAM GAIN1
B GAM GAIN1
R GAM GAIN2
B GAM GAIN2
R GAM CTR2
B GAM CTR2
R GAM CTR1
B GAM CTR1
N.C.
PV
CC
B
γ
CONT
RGB
γ
CONT
R
γ
CONT
γ
AMP
γ
AMP
γ
AMP
BRT
CONT
CLP
CLP
CLP
CLP
S/H
S/H
S/H
S/H
S/H
S/H
S/H
S/H
S/H
GCA
EA
GCA
GCA
EA
EA
GAIN
CONT
SW
BUFF
SW
BUFF
SW
BUFF
BUFF
SBRT
CONT
BUFF
BLKLMT
CTRL
PRG
SID
XV-C2E
31
2) Terminals
Terminal No.
Symbol
Remarks
1
RGB MBRT
4
R MBRT
5
B MBRT
7
GAM OUT
8
V
CC
1
9
RIN
10
GIN
11
BIN
12
GND
13
SID OUT
14
V
CC
2
15
R OUT
16
G OUT
17
B OUT
18
V
CC
3
22
GND
23
RGB SBRT
24
B SBRT
25
R SBRT
26
B CLP
27
G CLP
28
R CLP
29
SID CLP
Main brightness control terminal
common for RGB signals.
It is internally preset at 3.3V.
common for RGB signals.
It is internally preset at 3.3V.
Main brightness control terminal R
signal.
It is internally preset at 3.3V.
signal.
It is internally preset at 3.3V.
Main brightness control terminal B
signal.
It is internally preset at 3.3V.
signal.
It is internally preset at 3.3V.
G signal output terminal where the
reference signal is inserted and the
main brightness and gamma are
mixed.
reference signal is inserted and the
main brightness and gamma are
mixed.
5V power supply terminal.
R signal input signal.
Input 0.7Vp-p signal.
Input 0.7Vp-p signal.
G signal input signal.
Input 0.7Vp-p signal.
Input 0.7Vp-p signal.
B signal input signal.
Input 0.7Vp-p signal.
Input 0.7Vp-p signal.
GND terminal.
SID signal output terminal.
13V power supply terminal.
R signal output terminal.
G signal output terminal.
B signal output terminal.
5V power supply terminal.
GND terminal.
Supply control terminal common for
RGB signals.
RGB signals.
Supply control terminal for B signal.
It is internally preset at 3.3V.
It is internally preset at 3.3V.
Supply control terminal for R signal.
It is internally preset at 3.3V.
It is internally preset at 3.3V.
B output detection signal input
terminal.
terminal.
G output detection signal input
terminal.
terminal.
R output detection signal input
terminal.
terminal.
SID output detection signal input
terminal.
Use an external capacitor for
average value detection which has
a smaller absolute value and less
fluctuation.
terminal.
Use an external capacitor for
average value detection which has
a smaller absolute value and less
fluctuation.
SID output amplitude control
terminal.
It is internally preset at 3.3V.
terminal.
It is internally preset at 3.3V.
Level control terminal for RGB
signals to be inserted in SID signal.
signals to be inserted in SID signal.
FRP input terminal.
The polarity of RGB output is
reversed by this pulse. When it is
set at LOW, the polarity is reversed
and when it is set at HIGH, the
polarity is not reversed.
The polarity of RGB output is
reversed by this pulse. When it is
set at LOW, the polarity is reversed
and when it is set at HIGH, the
polarity is not reversed.
Input level
HIGH
>
4V
LOW
<
1V
FRP input terminal for SID output
The polarity of SID output is
reversed by this pulse. When it is
set at LOW, the polarity is reversed
and when it is set at HIGH, the
polarity is not reversed.
The polarity of SID output is
reversed by this pulse. When it is
set at LOW, the polarity is reversed
and when it is set at HIGH, the
polarity is not reversed.
Input level
HIGH
>
4V
LOW
<
1V
GND terminal
PRG pulse input terminal.
The PRG signal is inserted in SID
output by this pulse.
The PRG signal is inserted in SID
output by this pulse.
Input level
HIGH
>
4V
LOW
<
1V
VCOM voltage control terminal.
The variable range of VCOM
voltage covers -0.8V~1.3V to signal
center voltage.
The variable range of VCOM
voltage covers -0.8V~1.3V to signal
center voltage.
RGB and SID center voltage
control terminal.
control terminal.
VCOM voltage output terminal.
Limiter control terminal to limit the
RGB signal output amplitude.
It is internally preset at 3.3V.
RGB signal output amplitude.
It is internally preset at 3.3V.
Terminal to control the center of
RGB signal output limiter.
It is internally preset at 3.3V. When
it is preset, the limiter center
becomes equal to RGB center.
RGB signal output limiter.
It is internally preset at 3.3V. When
it is preset, the limiter center
becomes equal to RGB center.
RGB signal white peak limiter
control terminal.
It is internally preset at 3.3V.
control terminal.
It is internally preset at 3.3V.
Gamma circuit control terminal.
When it is set at HIGH, the gamma
circuit becomes effective and when
it is set at LOW, the gamma circuit
becomes ineffective.
When it is set at HIGH, the gamma
circuit becomes effective and when
it is set at LOW, the gamma circuit
becomes ineffective.
Input level
HIGH
>
4V
LOW
<
1V
30
SID CTR
31
PRG CTR
32
FRP
33
SID FRP
34
GND
35
PRG
36
VCOM CTR
37
SIG CENT
CTR
CTR
38
VCOM OUT
39
BLK LIM
40
BLK CENT
41
WHT LIM
42
GAM SEL
Terminal No.
Symbol
Remarks
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