Sharp AR-FN5 (serv.man3) Service Manual ▷ View online
3. CPU (H8S/2350)
3.1. General
The CPU controls the finisher loads and controls the system by send-
ing/receiving commands to/from the machine MCU PWB through the
serial communication line.
ing/receiving commands to/from the machine MCU PWB through the
serial communication line.
3.2. Features
The H8S/2350 is a microcomputer based on the H8S/2000 CPU, in
which the peripheral functions required for the system are integrated.
which the peripheral functions required for the system are integrated.
The H8S/2000 CPU is of internal 32bit composition, and is equipped
with the general-purpose registers of 16bit x 16 and the simple, opti-
mized command set with high-speed operations. It can handle 16MB
linear address space.
with the general-purpose registers of 16bit x 16 and the simple, opti-
mized command set with high-speed operations. It can handle 16MB
linear address space.
Its major functions include the DMA controller (DMAC), the bus mas-
ter of the data transfer controller (DTC), RAM, memory, the 16bit timer
pulse unit (TPU), the programmable pulse generator (PPG), the watch
dog timer (WDT), the serial communication interface (SCI), the A/D
converter, the D/A converter, the I/O port, and other peripheral func-
tions.
ter of the data transfer controller (DTC), RAM, memory, the 16bit timer
pulse unit (TPU), the programmable pulse generator (PPG), the watch
dog timer (WDT), the serial communication interface (SCI), the A/D
converter, the D/A converter, the I/O port, and other peripheral func-
tions.
3.3. Pin configuration
MD2
MD1
MD0
PG2/CS2
PG1/CS3
PG0/CAS
P17/PO15/TIOCB2/TCLKD
P16/PO14/TIOCA2
P15/PO13/TIOCB1/TCLKC
P14/PO12/TIOCA1
P13/PO11/TIOCD0/TCLKB
P12/PO10/TIOCC0/TCLKA
P12/PO10/TIOCC0/TCLKA
P11/PO9/TIOCB0/DACK1
P10/PO8/TIOCA0/DACK0
P10/PO8/TIOCA0/DACK0
VREF
AVCC
AVSS
P40/AN0
P41/AN1
P42/AN2
P43/AN3
P44/AN4
P45/AN5
P41/AN1
P42/AN2
P43/AN3
P44/AN4
P45/AN5
P46/AN6/DA0
P47/AN7/DA1
P47/AN7/DA1
VSS
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
PE0/D0
PE1/D1
PE2/D2
PE3/D3
PE4/D4
PE5/D5
PE6/D6
PE7/D7
PD1/D9
PD2/D10
PD3/D11
PD4/D12
PD5/D13
PD6/D14
PD7/D15
PD0/D8
P30/TXD0
P31/TXD1
P32/RXD0
P33/RXD1
P34/SCK0
P35/SCK1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
VCC
VSS
VCC
VSS
EX
TA
L
XTAL
NMI
WDTOVF
RES
STBY
PF7/
φ
PF0/BRE
Q
PF1/BA
CK
PF2/LCAS/
W
AIT/BREQ0
PF3/LWR
PF4/HWR
PF5/RD
PF6/AS
P62/DREQ1
P63/TEND1
P60/DREQ0
/CS4
P61/TEND0/CS5
P27/PO7/TIOCB5
P26/PO6/TIOCA5
P25/PO5/TIOCB4
P24/PO4/TIOCA4
P23/PO3/TIOCD3
P22/PO2/TIOCC3
P21/PO1/TIOCB3
P20/PO0/TIOCA3
VC
C
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
P52
P51
P50
P53/ADTRG
102
101
100
99
98
97
69
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
VC
C
PG4/CS0
PG3/CS1
P64/IRQ0
P65/IRQ1
P67/CS7/IRQ3
P66/CS6/IRQ2
PA
0/A16
PA
1/A17
PA
2/A18
PA
3/A19
PA4/A20/I
R
Q4
PA5/A21/I
R
Q5
PA6/A22/I
R
Q6
PA7/A23/I
R
Q7
PB
0/A8
PB
1/A9
PB
2/A10
PB
3/A11
PB
4/A12
PB
5/A13
PB
6/A14
PB
7/A15
PC
0/A
0
PC
1/A
1
PC
2/A
2
PC
3/A
3
PC
4/A
4
PC
5/A
5
PC
6/A
6
PC
7/A
7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
VS
S
VS
S
VS
S
VC
C
VS
S
VS
S
VS
S
VS
S
3.4. CPU H8S2350 port table
Pin No.
Signal name
CPU operation mode
Input/Output
Function
Logic
1
CS1
/CS1
Output
Chip Select
L; Select
2
CS0
/CS0
Output
Chip Select
L; Select
3
Vss
Vss
Power
Power
GND
4
NC
NC
NC
NC
GND
5
Vcc
Vcc
Power
Power
5V
6
A0
A0
Output
System Bus (Address)
7
A1
A1
Output
System Bus (Address)
8
A2
A2
Output
System Bus (Address)
9
A3
A3
Output
System Bus (Address)
10
Vss
Vss
Power
Power
GND
11
A4
A4
Output
System Bus (Address)
12
A5
A5
Output
System Bus (Address)
13
A6
A6
Output
System Bus (Address)
14
A7
A7
Output
System Bus (Address)
15
A8
A8
Output
System Bus (Address)
16
A9
A9
Output
System Bus (Address)
17
A10
A10
Output
System Bus (Address)
18
A11
A11
Output
System Bus (Address)
19
Vss
Vss
Power
Power
GND
20
A12
A12
Output
System Bus (Address)
21
A13
A13
Output
System Bus (Address)
22
A14
A14
Output
System Bus (Address)
23
A15
A15
Output
System Bus (Address)
24
A16
A16
Output
System Bus (Address)
25
A17
A17
Output
System Bus (Address)
Not Used
26
A18
A18
Output
System Bus (Address)
Not Used
27
A19
A19
Output
System Bus (Address)
Not Used
28
Vss
Vss
Power
Power
GND
29
A20
A20
Output
System Bus (Address)
Not Used
30
/T2OD#
PA5, /IRQ5
Input
Tray2 Paper Out Sensor
L; Paper Detect
31
CASW#
PA6, /IRQ6
Input
Cartridge Switch
H; No Cartridge
32
/SEPL#
PA7, /IRQ7
Input
Self Priming Sensor
L; Ready
33
STHP#
P67, /IRQ3
Input
HP Sensor
L; Home Position
34
SNSW
P66, /IRQ2
Input
Stapler Needle Switch
H; No Needle
35
Vss
Vss
Power
Power
GND
36
Vss
Vss
Power
Power
GND
37
WDPD#
P65, /IRQ1
Input
Paper Wide Detect
L; Paper Detect
38
INPD#
P64, /IRQ0
Input
Paper in Sensor
L; Paper Detect
39
Vcc
Vcc
Power
Power
5V
40
STM+
PE0
Output
Stapler Motor Control
H; ON(+)
41
STM-
PE1
Output
Stapler Motor Control
H; ON(-)
42
LUM+
PE2
Output
Lift Up Motor Control
H; ON(+)
43
LUM-
PE3
Output
Lift Up Motor Control
H; ON(-)
44
Vss
Vss
Power
Power
GND
45
OFM+
PE4
Output
Offset Motor Control
H; ON(+)
46
OFM-
PE5
Output
Offset Motor Control
H; ON(-)
47
GLSL1
PE6
Output
Gate-L Solenoil Drive
H; ON(1)
48
GLSL2
PE7
Output
Gate-L Solenoil Drive
H; ON(2)
49
D0
D8
Bi-Directional
System Bus (DATA)
50
D1
D9
Bi-Directional
System Bus (DATA)
51
D2
D10
Bi-Directional
System Bus (DATA)
52
D3
D11
Bi-Directional
System Bus (DATA)
53
Vss
Vss
Power
Power
GND
54
D4
D12
Bi-Directional
System Bus (DATA)
55
D5
D13
Bi-Directional
System Bus (DATA)
56
D6
D14
Bi-Directional
System Bus (DATA)
57
D7
D15
Bi-Directional
System Bus (DATA)
58
Vcc
Vcc
Power
Power
5V
59
FINCMD
TxD0
Output
60
FMMD
P31
Output
Main Motor Current Control
H; Low
61
FINSTS
RxD0
Input
62
BKMD
P33
Output
Back Motor Current Control
H; Low
63
SDMD
P34
Output
Side Motor Current Control
H; Low
Pin No.
Signal name
CPU operation mode
Input/Output
Function
Logic
64
DCCON
P35
Output
DC Motor ON/OFF Control
H; ON
65
Vss
Vss
Power
Power
GND
66
reserve
P60
67
Vss
Vss
Power
Power
GND
68
Vss
Vss
Power
Power
GND
69
/T1OD#
P61
Input
Tray1 Paper Out Sensor
L; Paper Detect
70
STSL
P62
Output
Shutter Solenoid Drive
H; ON
71
AJSL
P63
Output
Adjust Solenoid Drive
H; ON
72
FMM/B
P27
Output
Main Motor Drive
73
FMM/A
P26
Output
Main Motor Drive
74
FMMB
P25
Output
Main Motor Drive
75
FMMA
P24
Output
Main Motor Drive
76
SDM/B
P23
Output
Side Control Motor Drive
77
SDM/A
P22
Output
Side Control Motor Drive
78
SDMB
P21
Output
Side Control Motor Drive
79
SDMA
P20
Output
Side Control Motor Drive
80
N.C.
/WDTOVF
Output
Watch Dog Timer Overflow
81
/RES
/RES
Input
Master Reset
L; RESET
82
N.C.
NMI
Input
Not Used
83
N.C.
/STBY
Input
Not Used
84
Vcc
Vcc
Power
Power
5V
85
XTAL
XTAL
Input
Oscilator Input
86
EXTAL
EXTAL
Input
Oscilator Input
87
Vss
Vss
Power
Power
GND
88
/RCSREADY
PF7
Input
89
Vcc
Vcc
Power
Power
5V
90
N.C.
/AS
Output
Address Strobe
91
/RD
/RD
Output
Read Strobe
L; Active
92
/HWR
/HWR
Output
High Write Strobe
L; Active
93
N.C.
/LWR
Output
Low Write Strobe
94
RD/BY
PF2
Input
Lady/Busy Signal
95
/FINCRDY#
PF1
Input
L; Active
96
/FINSRDY#
PF0
Output
L; Active
97
/OFSL
P50
Output
Offset Solenoid Drive
L; ON
98
/ORCL
P51
Output
P-Out Roller Clutch
L; ON
99
Vss
Vss
Power
Power
GND
100
Vss
Vss
Power
Power
GND
101
GRSL
P52
Output
Gate-R Solenoil Drive
L; ON
102
BKSL
P53
Output
Back Solenoid Drive
L; ON
103
Vcc
AVcc
Power
Power (Analog)
5V
104
Vcc
Vref
Reference
Reference Voltage
5V
105
SDHP#
P40
Input
Side Motor HP Sensor
H; Home Position
106
BKHP#
P41
Input
Back Motor HP Sensor
H; Home Position
107
T2UP#
P42
Input
Tray2 Up sensor
L, L; Up
108
T2DN#
P43
Input
Tray2 Down sensor
L, H; Down
109
T1PD#
P44
Input
Tray1 Paper Position Sensor
L; Paper Detect
110
T2PD#
P45
Input
Tray2 Paper Position Sensor
L; Paper Detect
111
reserve
P46
112
ATPD#
P47
Input
Adjust Tray Paper Sensor
H; Paper Detect
113
Vss
AVss
Power
Power (Analog)
GND
114
Vss
Vss
Power
Power
GND
115
BKM/B
P17
Output
Back Control Motor Drive
116
BKM/A
P16
Output
Back Control Motor Drive
117
BKMB
P15
Output
Back Control Motor Drive
118
BKMA
P14
Output
Back Control Motor Drive
119
OFHP#
P13
Input
Offset Motor Home Position
H; Home Position
120
LUEN#
P12
Input
Lift Up Encorder Sensor
121
reserve
P11
122
reserve
P10
123
MD0
MD0
Input
Mode Select 0
H
124
MD1
MD1
Input
Mode Select 1
L
125
MD2
MD2
Input
Mode Select 2
H
126
TCSW
PG0
Input
Tray Cover Monitor
L; Open
127
SCSW
PG1
Input
Stapler Cover Monitor
L; Open
128
PGSW
PG2
Input
PG Cover Monitor
L; Open
4. I/F circuit and reset circuit
This unit performs serial communication with the copier in the ad-
vancement synchronization mode where synchronization is made in
the unit of a character.
vancement synchronization mode where synchronization is made in
the unit of a character.
The signal (FINSTS) sent from the machine and the communication
allow signal (/FINCRDY) are received by the CPU on the finisher side
through the buffer circuit. Similarly, the send signal (FINCMD) from
the finisher and the communication allow signal (/FINSRDY) are re-
ceived by the CPU on the machine through the buffer IC 74VHC244
(IC104).
allow signal (/FINCRDY) are received by the CPU on the finisher side
through the buffer circuit. Similarly, the send signal (FINCMD) from
the finisher and the communication allow signal (/FINSRDY) are re-
ceived by the CPU on the machine through the buffer IC 74VHC244
(IC104).
Similarly, the reset signal is passed to the CPU reset pin on the
finisher side through the IC105.
finisher side through the IC105.
Signal name
Content
Logic (Connector level)
FINSTS
Line of signals sent from the copier to the finisher
H: Start bit detected
L: Normal (Mark state)
L: Normal (Mark state)
FINCMD
Line of signals sent from the finisher to the copier
L: Start bit detected
H: Normal (Mark state)
H: Normal (Mark state)
/FINCRDY
Line of signal which indicates the status of the communication request answer when
sending signals from the finisher to the copier
sending signals from the finisher to the copier
H: Communication disable
L: Communication enable
L: Communication enable
/FINSRDY
Line of signal which indicates the status of the communication request when sending
signals from the finisher to the copier
signals from the finisher to the copier
H: No request for communication
L: Communication request state
L: Communication request state
/RES
Line of hard reset signal from the copier
L: Reset state
H: Reset cancel state
H: Reset cancel state
5V
5V
5V
5V
5V
1A1
2
1A2
4
1A3
6
1A4
8
2A1
11
2A2
13
2A3
15
2A4
17
1G
1
2G
19
1Y1
18
1Y2
16
1Y3
14
1Y4
12
2Y1
9
2Y2
7
2Y3
5
2Y4
3
20
GND
10
1
8
2
7
3
6
4
5
1
8
2
7
3
6
4
5
1A1
2
1A2
4
1A3
6
1A4
8
2A1
11
2A2
13
2A3
15
2A4
17
1G
1
2G
19
1Y1
18
1Y2
16
1Y3
14
1Y4
12
2Y1
9
2Y2
7
2Y3
5
2Y4
3
VCC
20
GND
10
BR1
10kX4
10kX4
R141
4.7k
4.7k
reserve
/RES
FINSTS#
/FINCRDY#
P60
/RES
RxD0
PF1
C145
1000pF/50V
1000pF/50V
C139
22000pF/25V
IC105
74VHCT244M
C181
0.1uF/25V
0.1uF/25V
/RES
FINSTS
/FINCRDY
FINCMD
/FINSRDY
3.3V
IC104
VCC
74VHC244M
C180
0.1uF/25V
C146
1000pF/50V
1000pF/50V
TxD0
PF0
FINCMD#
/FINSRDY#
BR2
10kX4
10kX4
R142
4.7k
4.7k
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