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In the communication buffer circuit, the transmission signal (F-TXD)
and communication permit signal (F-DTR) from the copier is received
by the transistor array TD62504 (IC14), while the reception signal
(F-RXD) and communication request signal (F-DSR) transmitted from
the finisher to the copier is output from the IC14.

The reset signal from the copier is also received by the IC14 and
input to the CPU’s reset terminal (active at L). In addition, the rever-
sion signal is input to the expansion I/O reset terminal (active at H).
For each signal, a protective diode is inserted between 

+

5V and

GND.

Signal

name

Description

Logic (connector level)

F-TXD

Signal line from copier to finisher

Start bit detection at H
Usual (marking state) at L

F-RXD

Signal line from finisher to copier

Start bit detection at L

Usual (marking state) at L

F-DTR

Status display signal line for the signal showing communication permit
from finisher to copier

Communication from finisher to copier is inhibited at H
Communication from finisher to copier is permitted at L

F-DSR

Status display signal line for the signal showing communication request
from finisher to copier

No communication request from finisher to copier at H
Communication request from finisher to copier at L

F-RES

Hard rest signal from copier

Reset at H
Reset is released at L

CPU

(IC02)

I/O

(IC03)

RXD0/P92

TXD0/P90

P95

P94

RES

RESET

TD62504F

TD62504F

TD62504F

TD62504F

TD62504F

TD62504F

TD62504F

IC14

IC14

IC14

IC14

IC14

IC14

+5V

+5V

+5V

+5V

+5V

+5V

+5V

+5V

+5V

+5V

+5V

BR14-2
4.7K

BR14-6
4.7K

BR12-2
4.7K

R199

1K

R139
1K

3

14

7

10

BR14-7
4.7K

BR14-5
4.7K

BR12-6

4.7K

BR12-3
4.7K

BR14-3

4.7K

15

2

12

5

11

6

BR14-4

4.7K

13

4

IC14

16

1

+5V

BR12-5

4.7K

+5V

1SS133x5

0.1U

1SS133x5

RES/

RES

14

F-TXD

F-RXD

12

17

F-DTR

F-DSR

16

63

33

F-TXD

F-RXD

F-DTR

F-DSR

F-RES

C131
0.1U

D14 D18 D15 D17 D16

D9 D13 D10 D12 D11 C171

from Copier

The signal from each sensor is 10 kohm pull-up resistance, noise-re-
moving 1000 pF capacitor, 10 kohm protective resistance, CPU, and
expansion I/O input port. 

The sensor signal for transfer system is input to the schmitt trigger
input port because the sensor input circuit is not provided with rectifier
circuit.

+5V

+5V

1000PF

P**

10K

Ω

(IC02)

AMP

*1

*1:Rated Voltage Sircuit

CPU

+5V

+5V

1000PF

PA or PB

(IC03)

*2

I/O

10K

Ω

10K

Ω

10K

Ω

240

Ω

HP sensor

Transfer system sensor

*2 Schumit trigger input port

9 – 6

This circuit checks whether the finisher is connected to the copier,
both the top and front doors are opened. It is connected to mi-
croswitches whose contacts are closed when the finisher is con-
nected to the copier or the doors are closed. 

Each switch is connected in series from 

+

24V so that it becomes a

power supply switch for the drive. That is, 

+

24V is not conducted to

the drive if all the 3 microswitches are closed. 

When the finisher is connected to the copier, the microswitch turns
on, letting 

+

24V be applied to ZD4. This allows electric current to flow

to the base resistance of the transistor array TD62504 (IC19), thus
turning on the transistor to change the expansion I/O PG1 (DSW1
signal) to L level.

When the finisher is disconnected from the copier, the transistor is
turned off to change the expansion I/O PG1 to H level. ZD4 (RD6.2E)
has a threshold level preset, to increase detection speed when the
supply of 

+

24V is cut off. The levels of PG2 and 3 (DSW2, 3 signals)

also change when the top and front door switch is opened and
closed.

In addition, when 

+

24V power supply from the copier is cut off, the

expansion I/O PG0 (PWD signal) level changes at the above circuit.

Here are logic’s at the time of the power supply from the copier being
cut off and the doors opening and closing being detected.

←

Upper Lower

→

Status

Expansion

I/O port

PG0

PG1

PG2

PG3

Remarks

Signal

name

PWD

DSW1 DSW2 DSW3

Power supply from
copier is cut off

H

d.c

d.c

d.c

Disconnected from
copier

L

H

d.c

d.c

H:

Power supply cut off (door open)

L:

Conducting (door closed)

d.c: Unknown (no status is shown because power is cut off at up-

stream)

PWD    54
DSW1  55
DSW2  56
DSW3  57

BR10

10Kx5

O1
O2
O3
O4
O5
O6
O7

COM

I1
I2
I3
I4
I5
I6
I7
GND

TD62504F

IC19

16
15
14
13
12
11
10

9

PWD
DSW1
DSW2
DSW3

5
6
7
8

+5V

(IC03)

PG0
PG1
PG2
PG3

RD6.2EB2

ZD05

RD6.2EB2

ZD04

RD6.2EB2

ZD03

RD6.2EB2

ZD06

+24VIN

+24V1

+24V1

+24V2

+24V2

+24V

+24V

I/O

2 3 4 5 6

4

3

2

1

Power supply +24V

Upper

Lower

Copier connection sw

Upper door sw

to each motor and
solenoid clutch

Finisher door monitoring circuit

Front door sw

Microswitch x 3

Normal: SW ON
Copier separated
or door open: SW OFF

9 – 7

The solenoid and clutch drive circuit uses non-inversion transistor
arrays TD62318AP (IC17, 18) which turn on the solenoids and
clutches when the input signal is at L; and an inversion transistor
array TD62004AP (IC5) which turns on the solenoids and clutches
when the input signal is at H.

The expansion I/O PG port which controls the solenoids and clutches
is an open collector type which becomes high impedance when reset-
ting and H output. For this reason, to turn on the solenoids and
clutches at L level, the non-inversion type TD62318AP is used for
driving the PG port. On the other hand, the expansion I/O’s PC port is
at L level at resetting. For this reason, for driving the PC port, the
inversion type TD62004AP which turns on the solenoids and clutches
at H level is used.

The jogger motor control signal (JMA, A/, B. B/) from the expansion
I/O (IC3) is input into the driver IC TD62004AP (IC8), to drive the
jogger stepping motor which aligns the sheets sidewise.

The driving method is unipolar, 1-2 phase excitement, constant-volt-
age method.

Here is the driving pattern for the jogger motor.

(IC03)

PF0
PF1
PF2
PF3

59  INGSL/
60  T3UPSL/
61  OG1SL/
62  OG3SL/

PC4
PC5
PC6
PC7

49  SPSL
48  STSL

47  OG2SL

46  WLCL

PF4
PF5
PF6
PF7

63  RRSL/
64  T12CL/

1  PDCL/

2  STORCL/

1

2
3
4
5
6
7
8

13

4
5

12

13

4
5

12

14

11

6

3

14

11

6

3

16
15
14

13
12
11

10

9

I1
I2
I3
I4
I5
I6
I7
GND

COM

O1
O2
O3
O4
O5
O6

O7

IC05

TD62004AP

IC17

IC18

TD62318AP

8

16

9

1

15

10

7

2

I4

I3

I2

I1

O4

O3

O2

O1

VCC2

VCC1

COM2

COM1

GND

GND

GND

GND

8

16

9
1

15

10

7

2

I4

I3

I2

I1

O4

O3

O2

O1

VCC2

VCC1

COM2

COM1

GND

GND

GND

GND

TD62318AP

+24V

RD16FB

RD16FB

ZD02

ZD08

+5V

+24V

+5V

+24V

SPSL/

STSL/

OG2SL/

WLCL/

INGSL/

T3UPSL/

OG1SL/
OG3SL/

RRSL/

T12CL/

PDCL/

STORCL/

+24V

+24V

+24V

I/0

RRSL
T12CL
PDCL

STORCL

OG3SL

OG1SL

T3UPSL

INGSL

WLCL

OG2SL

STSL

SPSL

I/O

PC0

PC3

(IC03)

50

53

52

51

PC2

PC1

JMA
JMA/

JMB
JMB/

1
2
3
4

I1

5

7

6

8

I2
I3
I4
I5
I6
I7
GND

IC08

TD62004AP

O1
O2
O3
O4
O5
O6
O7

COM

9
16
15
14
13

11

12

10

N.C.
N.C.
N.C.

N.C.
N.C.

N.C.

R13

2.4K(1/4W)

JGMA

JGMA/
JGMB

JGMB/

+24V

JGM

+24V

+24V

JMA

JMB

JMA/

JMB/

Alignment direction

Stop

Opening direction

9 – 8

The pusher motor control signal (PMA, A/, B, B/), reversion motor
control signal (RMA, A/, B, B/) and staple unit movement motor con-
trol signal (STUMA, A/, B, B/) from the CPU (IC21) is input to the
stepping motor driver IC SLA7024M (IC11, 4, 7), to drive the following
motors: the pusher motor which elevates the paper  inside the staple
tray to the stapling position and paper discharge position; the rever-
sion motor which reverses the paper; and the staple unit movement
motor which move the staple unit to the stapling position.

The driving method is a unipolar, 2-phase (pusher), 1-2 phase (rever-
sion, staple unit movement), constant-current chopper driving
method.

When the paper is stored inside the staple tray by static excitement
onto the pusher motor, the PMPD signal from the CPU is made at H
level to set the motor power down mode, in order to suppress heat
buildup (usually set to about 50% of the motor drive current).

Here are the driving patterns for the pusher, reversion, staple unit
movement motors.

PMA

PMB

PMA/

PMB/

Up

Stop

Energized  

Down

RMA

RMB

RMA/

RMB/

Reversion unit paper
entry direction

Stop

Reversion unit paper
discharge direction

STUMA

STUMB

STUMA/

STUMB/

Front direction

Stop

Rear direction

CPU

PB0

PB3

(IC02)

2

5

4

3

PB2

PB1

RMA
RMA/
RMB
RMB/

3

14

10

6

REFA

5

16

17

REFB
RSB
IN A

IN/A
IN B

IN/B

IC04

SLA7024MT

OUT A

OUT/A
OUT B

OUT/B

GA
GB

VSA 7

1

8

11
18

4

15

RVMA
RVMA/
RVMB
RVMB/

+24V

12

VSB

2

9

13

TDA
TDB
RSA

R142

47K

C132

470P

C136

470P

+5V

C04 47U/35V

RVM

+24V

+24V

R146

47K

C135

2200P

R01

1(1W)

R145

2.4K

R02

1(1W)

R144

2.4K

C134

2200P

R143

0.1U

C133

100

R141

910

+5V

PB4

PB7

58

9

8

7

PB6

PB5

PMA
PMA/

PMB
PMB/

3

14

10

6

REFA

5

16

17

REFB
RSB
IN A
IN/A
IN B
IN/B

IC11

SLA7024MT

OUT A

OUT/A
OUT B

OUT/B

GA
GB

VSA 7

1

8

11
18

4

15

PSMA
PSMA/
PSMB
PSMB/

+24V

12

VSB

2

9

13

TDA
TDB
RSA

R154

47K

C143

470P

C147

470P

+5V

C05

47U/35V

PSM

+24V

+24V

R159

47K

C146

2200P

R14

1(2W)

R157

2.4K

R15

1(2W)

R156

2.4K

C145

2200P

R155

0.1U

C144

200

R158

910

+5V

IC05

TD62004AP

10

7

P40

P43

18

21

20

19

P42

P41

STUMA
STUMA/

STUMB
STUMB/

3

14

10

6

REFA

5

16

17

REFB
RSB

IN A
IN/A
IN B

IN/B

IC07

SLA7024MT

OUT A

OUT/A
OUT B

OUT/B

GA
GB

VSA 7

1

8

11
18

4

15

STUMA
STUMA/
STUMB
STUMB/

+24V

12

VSB

2

9

13

TDA
TDB
RSA

R148

47K

C138

470P

C142

470P

+5V

C03 47U/35V

STUM

+24V

+24V

R152

47K

C141

2200P

R11

1(1W)

R151

2.4K

R12

1(1W)

R150

2.4K

C140

2200P

R149

0.1U

C139

160

R147

910

+5V

6

P60

PMPD

R153

200

Reversion motor driving circuit

Pusher motor driving circuit

Staple unit moving motor driving circuit

9 – 9