Sharp AR-FN1 (serv.man10) Service Manual ▷ View online
D. Expansion I/O: M66500FP (IC3) terminal signals
Pin
No.
Port
Signal
name
IN/OUT
ACTIVE
Specifications
Remarks
1
PF6
PDCL/
OUT
L
Puddler clutch drive signal (On at L)
2
PF7
STORCL/
OUT
L
Paper discharge roller pressure release clutch (On at L)
3
VCC
VCC
Power supply (
+
5V)
4
PE0
EMA
OUT
H
Elevator motor CW drive signal
5
PE1
EMB
OUT
H
Elevator motor CCW drive signal
6
PE2
N.C
7
PE3
N.C
8
PE4
STMA
OUT
H
Staple motor CW drive signal
9
PE5
STMB
OUT
H
Staple motor CCW drive signal
10
PE6
N.C
11
PE7
N.C
12
GND
GND
Power supply (GND)
13
PB0
STID/
IN
L
Staple tray paper entry sensor signal (On at L)
14
PB1
STPD/
IN
L
Staple tray paper sensor signal (On at L)
15
PB2
T1PF/
IN
L
Tray 1 paper full sensor signal (On at L)
16
PB3
N.C
17
PB4
T3UP
IN
H
Tray 3 upper limit sensor signal (On at H)
18
PB5
T3DN
IN
H
Tray 3 lower limit sensor signal (On at H)
19
PB6
LSTS/
IN
L
Stapler needle sensor signal (presence of needle at L)
20
PB7
NCTS/
IN
L
Stapler cartridge sensor signal (presence of cartridge at L)
21
PA7
T3OD/
IN
L
Tray 3 paper discharge sensor signal (On at L)
22
PA6
PFD4/
IN
L
Transfer sensor signal 4 (On at L)
23
PA5
PFD3/
IN
L
Transfer sensor signal 3 (On at L)
24
PA4
PFD2/
IN
L
Transfer sensor signal 2 (On at L)
25
PA3
PFD1/
IN
L
Transfer sensor signal 1 (On at L)
26
PA2
PGOP
IN
H
Upper transfer PG opening and closing detection signal (Open at H)
27
PA1
RVPD/
IN
L
Reversion paper discharge sensor signal (On at L)
28
PA0
INPD/
IN
L
Paper entry sensor signal (On at L)
29
VCC
VCC
Power supply (
+
5V)
30
/RD
RD/
IN
L
Data read signal (read at L)
31
/WR
WR/
IN
L
Data write signal (write at L)
32
/CS
CS/
IN
L
Chip select signal (select at L)
33
RESET
RESET
IN
H
Reset signal (reset at H)
34
GND
GND
Power supply (GND)
35
A2
A2
IN
Address signal (A2)
36
A1
A1
IN
Address signal (A1)
37
A0
A0
IN
Address signal (A0)
38
D0
D0
IN/OUT
Data signal (D0)
39
D1
D1
IN/OUT
Data signal (D1)
40
D2
D2
IN/OUT
Data signal (D2)
41
D3
D3
IN/OUT
Data signal (D3)
42
D4
D4
IN/OUT
Data signal (D4)
43
D5
D5
IN/OUT
Data signal (D5)
44
D6
D6
IN/OUT
Data signal (D6)
45
D7
D7
IN/OUT
Data signal (D7)
46
PC7
T3SLCL
OUT
H
Tray 3 low speed clutch drive signal (On at H)
47
PC6
OG2SL
OUT
H
Paper discharge gate 2 solenoid (On at H)
48
PC5
T12CL
OUT
H
Tray 1/2 low speed clutch drive signal (On at L)
49
PC4
SPSL
OUT
H
Short path switching solenoid (On at H)
50
PC0
JMA
OUT
H
Jogger motor drive signal A
51
PC1
JMA/
OUT
H
Jogger motor drive signal /A
52
PC2
JMB
OUT
H
Jogger motor drive signal B
53
PC3
JMB/
OUT
H
Jogger motor drive signal /B
54
PG0
PWD
IN
H
Power supply shut-off monitoring signal (power shut-off at H)
55
PG1
DSW1
IN
H
Connection to copier detection signal (disconnection at H)
56
PG2
DSW2
IN
H
Upper door opening and closing detection signal (door open at H)
57
PG3
DSW3
IN
H
Front door opening and closing detection signal (door open at H)
58
GND
GND
Power supply (GND)
59
PF0
INGSL/
OUT
L
Paper entry gate solenoid drive signal (On at L)
60
PF1
T3UPSL/
OUT
L
Tray 3 paper full defector drive solenoid signal (On at L)
61
PF2
OG1SL/
OUT
L
Paper discharge gate 1 solenoid drive signal (On at L)
62
PF3
OG3SL/
OUT
L
Paper discharge gate 3 solenoid drive signal (On at L)
63
PF4
RRSL
OUT
L
Reversion roller pressure release solenoid drive signal (On at L)
64
PF5
T30RCL/
OUT
L
Tray 3 high speed clutch drive signal (On at L)
9 – 5
5. Communication buffer and reset circuit
In the communication buffer circuit, the transmission signal (F-TXD)
and communication permit signal (F-DTR) from the copier is received
by the transistor array TD62504 (IC14), while the reception signal
(F-RXD) and communication request signal (F-DSR) transmitted from
the finisher to the copier is output from the IC14.
and communication permit signal (F-DTR) from the copier is received
by the transistor array TD62504 (IC14), while the reception signal
(F-RXD) and communication request signal (F-DSR) transmitted from
the finisher to the copier is output from the IC14.
The reset signal from the copier is also received by the IC14 and
input to the CPU’s reset terminal (active at L). In addition, the rever-
sion signal is input to the expansion I/O reset terminal (active at H).
For each signal, a protective diode is inserted between
input to the CPU’s reset terminal (active at L). In addition, the rever-
sion signal is input to the expansion I/O reset terminal (active at H).
For each signal, a protective diode is inserted between
+
5V and
GND.
Signal
name
Description
Logic (connector level)
F-TXD
Signal line from copier to finisher
Start bit detection at H
Usual (marking state) at L
Usual (marking state) at L
F-RXD
Signal line from finisher to copier
Start bit detection at L
Usual (marking state) at L
F-DTR
Status display signal line for the signal showing communication permit
from finisher to copier
from finisher to copier
Communication from finisher to copier is inhibited at H
Communication from finisher to copier is permitted at L
Communication from finisher to copier is permitted at L
F-DSR
Status display signal line for the signal showing communication request
from finisher to copier
from finisher to copier
No communication request from finisher to copier at H
Communication request from finisher to copier at L
Communication request from finisher to copier at L
F-RES
Hard rest signal from copier
Reset at H
Reset is released at L
Reset is released at L
CPU
(IC02)
I/O
(IC03)
RXD0/P92
TXD0/P90
P95
P94
RES
RESET
TD62504F
TD62504F
TD62504F
TD62504F
TD62504F
TD62504F
TD62504F
IC14
IC14
IC14
IC14
IC14
IC14
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
BR14-2
4.7K
4.7K
BR14-6
4.7K
4.7K
BR12-2
4.7K
4.7K
R199
1K
R139
1K
1K
3
14
7
10
BR14-7
4.7K
4.7K
BR14-5
4.7K
4.7K
BR12-6
4.7K
BR12-3
4.7K
4.7K
BR14-3
4.7K
15
2
12
5
11
6
BR14-4
4.7K
13
4
IC14
16
1
+5V
BR12-5
4.7K
+5V
1SS133x5
0.1U
1SS133x5
RES/
RES
14
F-TXD
F-RXD
12
17
F-DTR
F-DSR
16
63
33
F-TXD
F-RXD
F-DTR
F-DSR
F-RES
C131
0.1U
0.1U
D14 D18 D15 D17 D16
D9 D13 D10 D12 D11 C171
from Copier
6. Sensor input circuit
The signal from each sensor is 10 kohm pull-up resistance, noise-re-
moving 1000 pF capacitor, 10 kohm protective resistance, CPU, and
expansion I/O input port.
moving 1000 pF capacitor, 10 kohm protective resistance, CPU, and
expansion I/O input port.
The sensor signal for transfer system is input to the schmitt trigger
input port because the sensor input circuit is not provided with rectifier
circuit.
input port because the sensor input circuit is not provided with rectifier
circuit.
+5V
+5V
1000PF
P**
10K
Ω
(IC02)
AMP
*1
*1:Rated Voltage Sircuit
CPU
+5V
+5V
1000PF
PA or PB
(IC03)
*2
I/O
10K
Ω
10K
Ω
10K
Ω
240
Ω
HP sensor
Transfer system sensor
*2 Schumit trigger input port
9 – 6
7. Switch input circuit
This circuit checks whether the finisher is connected to the copier,
both the top and front doors are opened. It is connected to mi-
croswitches whose contacts are closed when the finisher is con-
nected to the copier or the doors are closed.
both the top and front doors are opened. It is connected to mi-
croswitches whose contacts are closed when the finisher is con-
nected to the copier or the doors are closed.
Each switch is connected in series from
+
24V so that it becomes a
power supply switch for the drive. That is,
+
24V is not conducted to
the drive if all the 3 microswitches are closed.
When the finisher is connected to the copier, the microswitch turns
on, letting
on, letting
+
24V be applied to ZD4. This allows electric current to flow
to the base resistance of the transistor array TD62504 (IC19), thus
turning on the transistor to change the expansion I/O PG1 (DSW1
signal) to L level.
turning on the transistor to change the expansion I/O PG1 (DSW1
signal) to L level.
When the finisher is disconnected from the copier, the transistor is
turned off to change the expansion I/O PG1 to H level. ZD4 (RD6.2E)
has a threshold level preset, to increase detection speed when the
supply of
turned off to change the expansion I/O PG1 to H level. ZD4 (RD6.2E)
has a threshold level preset, to increase detection speed when the
supply of
+
24V is cut off. The levels of PG2 and 3 (DSW2, 3 signals)
also change when the top and front door switch is opened and
closed.
closed.
In addition, when
+
24V power supply from the copier is cut off, the
expansion I/O PG0 (PWD signal) level changes at the above circuit.
Here are logic’s at the time of the power supply from the copier being
cut off and the doors opening and closing being detected.
cut off and the doors opening and closing being detected.
←
Upper Lower
→
Status
Expansion
I/O port
PG0
PG1
PG2
PG3
Remarks
Signal
name
PWD
DSW1 DSW2 DSW3
Power supply from
copier is cut off
copier is cut off
H
d.c
d.c
d.c
Disconnected from
copier
copier
L
H
d.c
d.c
H:
Power supply cut off (door open)
L:
Conducting (door closed)
d.c: Unknown (no status is shown because power is cut off at up-
stream)
PWD 54
DSW1 55
DSW2 56
DSW3 57
DSW1 55
DSW2 56
DSW3 57
BR10
10Kx5
O1
O2
O3
O4
O5
O6
O7
O2
O3
O4
O5
O6
O7
COM
I1
I2
I3
I4
I5
I6
I7
GND
I2
I3
I4
I5
I6
I7
GND
TD62504F
IC19
16
15
14
13
12
11
10
15
14
13
12
11
10
9
PWD
DSW1
DSW2
DSW3
DSW1
DSW2
DSW3
5
6
7
8
6
7
8
+5V
(IC03)
PG0
PG1
PG2
PG3
PG1
PG2
PG3
RD6.2EB2
ZD05
RD6.2EB2
ZD04
RD6.2EB2
ZD03
RD6.2EB2
ZD06
+24VIN
+24V1
+24V1
+24V2
+24V2
+24V
+24V
I/O
2 3 4 5 6
4
3
2
1
Power supply +24V
Upper
Lower
Copier connection sw
Upper door sw
to each motor and
solenoid clutch
solenoid clutch
Finisher door monitoring circuit
Front door sw
Microswitch x 3
Normal: SW ON
Copier separated
or door open: SW OFF
Copier separated
or door open: SW OFF
9 – 7
8. Solenoid and clutch drive circuit
The solenoid and clutch drive circuit uses non-inversion transistor
arrays TD62318AP (IC17, 18) which turn on the solenoids and
clutches when the input signal is at L; and an inversion transistor
array TD62004AP (IC5) which turns on the solenoids and clutches
when the input signal is at H.
arrays TD62318AP (IC17, 18) which turn on the solenoids and
clutches when the input signal is at L; and an inversion transistor
array TD62004AP (IC5) which turns on the solenoids and clutches
when the input signal is at H.
The expansion I/O PG port which controls the solenoids and clutches
is an open collector type which becomes high impedance when reset-
ting and H output. For this reason, to turn on the solenoids and
clutches at L level, the non-inversion type TD62318AP is used for
driving the PG port. On the other hand, the expansion I/O’s PC port is
at L level at resetting. For this reason, for driving the PC port, the
inversion type TD62004AP which turns on the solenoids and clutches
at H level is used.
is an open collector type which becomes high impedance when reset-
ting and H output. For this reason, to turn on the solenoids and
clutches at L level, the non-inversion type TD62318AP is used for
driving the PG port. On the other hand, the expansion I/O’s PC port is
at L level at resetting. For this reason, for driving the PC port, the
inversion type TD62004AP which turns on the solenoids and clutches
at H level is used.
9. Jogger motor drive circuit
The jogger motor control signal (JMA, A/, B. B/) from the expansion
I/O (IC3) is input into the driver IC TD62004AP (IC8), to drive the
jogger stepping motor which aligns the sheets sidewise.
I/O (IC3) is input into the driver IC TD62004AP (IC8), to drive the
jogger stepping motor which aligns the sheets sidewise.
The driving method is unipolar, 1-2 phase excitement, constant-volt-
age method.
age method.
Here is the driving pattern for the jogger motor.
(IC03)
PF0
PF1
PF2
PF3
PF1
PF2
PF3
59 INGSL/
60 T3UPSL/
61 OG1SL/
62 OG3SL/
60 T3UPSL/
61 OG1SL/
62 OG3SL/
PC4
PC5
PC6
PC7
PC5
PC6
PC7
49 SPSL
48 STSL
48 STSL
47 OG2SL
46 WLCL
PF4
PF5
PF6
PF7
PF5
PF6
PF7
63 RRSL/
64 T12CL/
64 T12CL/
1 PDCL/
2 STORCL/
1
2
3
4
5
6
7
8
3
4
5
6
7
8
13
4
5
5
12
13
4
5
5
12
14
11
6
3
14
11
6
3
16
15
14
15
14
13
12
11
12
11
10
9
I1
I2
I3
I4
I5
I6
I7
GND
I2
I3
I4
I5
I6
I7
GND
COM
O1
O2
O3
O4
O5
O6
O2
O3
O4
O5
O6
O7
IC05
TD62004AP
IC17
IC18
TD62318AP
8
16
9
1
15
10
7
2
I4
I3
I2
I1
O4
O3
O2
O1
VCC2
VCC1
COM2
COM1
GND
GND
GND
GND
8
16
9
1
1
15
10
7
2
I4
I3
I2
I1
O4
O3
O2
O1
VCC2
VCC1
COM2
COM1
GND
GND
GND
GND
TD62318AP
+24V
RD16FB
RD16FB
ZD02
ZD08
+5V
+24V
+5V
+24V
SPSL/
STSL/
OG2SL/
WLCL/
INGSL/
T3UPSL/
OG1SL/
OG3SL/
OG3SL/
RRSL/
T12CL/
PDCL/
STORCL/
+24V
+24V
+24V
I/0
RRSL
T12CL
PDCL
T12CL
PDCL
STORCL
OG3SL
OG1SL
T3UPSL
INGSL
WLCL
OG2SL
STSL
SPSL
I/O
PC0
PC3
(IC03)
50
53
52
51
PC2
PC1
JMA
JMA/
JMA/
JMB
JMB/
JMB/
1
2
3
4
2
3
4
I1
5
7
6
8
I2
I3
I4
I5
I6
I7
GND
I3
I4
I5
I6
I7
GND
IC08
TD62004AP
O1
O2
O3
O4
O5
O6
O7
O2
O3
O4
O5
O6
O7
COM
9
16
15
14
13
16
15
14
13
11
12
10
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
R13
2.4K(1/4W)
JGMA
JGMA/
JGMB
JGMB
JGMB/
+24V
JGM
+24V
+24V
JMA
JMB
JMA/
JMB/
Alignment direction
Stop
Opening direction
9 – 8
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