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AR-CF2  ELECTRICAL SECTION  9 - 7

This circuit controls the flapper solenoid operation and the registration
clutch engagement.

When the signal F_SOL is "H", Q2 turns on to activate the solenoid.
Similarly, when the signal R_CL is "H", Q3 turns on to engage the
clutch.

The flapper solenoid drive signal is the PWM signal. At the beginning
of the solenoid activation, the signal is adjusted to set the solenoid at
100% duty cycle. After the plunger of the solenoid is pulled in, the sig-
nal is adjusted to set the solenoid at 70% duty cycle in order to reduce
the temperature rise with the plunger hold.

The circuit transmits a reset signal to the CPU when the power is
turned on or a power brownout is detected.

The circuit includes a watchdog timer intended to the CPU system
operation diagnosis.

After the power is turned on, normally IC3-Pin8 (*RES) is "H". How-
ever, when the +5V voltage falls to 4.2V or less because of the power
turned off or any trouble, IC3-Pin8 turns "L" to reset the CPU.

The clock signal from the CPU is transmitted to IC3-Pin3 (CK) at a reg-
ular interval to clear the watchdog timer embedded in IC3. However, if
the clock signal from the CPU disappears because of a system trouble,
IC3-Pin8 turns "L" to reset the CPU and stop the system operation.

This circuit consists of the data storage EEPROM and the peripheral
circuits.

IC4 is a storage memory for the adjustment settings of the reverse sen-
sor (reflective sensor) and the paper width detection potentiometer,
and passes the data to the CPU through the four-wire serial interface.

Once data is stored, the data is retained and not cleared even if the
power is turned off.

IC4-Pin1 (CS) is the chip selection terminal, and stays "H" during pass-
ing data.

IC4-Pin2 (SK) is the serial clock terminal. The serial data is transmitted
synchronizing with the clock signal input to the terminal

IC4-Pin3 (DI) is the serial data input terminal. IC4-Pin4 (DO) is the
serial data output terminal.

Registration CL

Flapper SOL

Not Mounted

AR-CF2  ELECTRICAL SECTION  9 - 8

This circuit limits an inrush current flowing into the regeneration capac-
itor included in the motor drive system to a certain value or less. The
circuit consists of the PTC thermistor (PTH2) that limits a current and
the FET (Q11) that allows a steady current flowing.

When the JAM cover open/closed detection switch is closed, the cath-
ode voltage of ZD1 starts rising to the zener voltage according to the
time constant of R55 and C46. During the rise of the cathode voltage,
Q11 is off because no base current to Q10 keeps Q10 off, and then a
current flows to PTH2 to charge the regeneration capacitor.

After the regeneration capacitor is fully charged, and the cathode volt-
age of ZD1 reaches over the zener voltage according to the time con-
stant of R55 and C46, Q11 is turned on because the base current from
ZD1 to Q10 turns Q10 on. And then the current flows to Q11 instead of
PTH2 to release the current limitation. The circuit consisting of PTH1
and D3 is intended to eliminate the electric charge accumulated in C46
immediately to limit an inrush current generated by momentary open-
ing and shutting of the cover.

This circuit includes the input circuits of the switches on the operator
panel and the drive circuits of the LEDs. 

The circuits connected to CN15-Pin1, 2, 3 are the input circuits of the
switches on the operator panel. The input signal from the switch goes
"L" when the switch is on, "H" when off.

The circuits connected to CN15-Pin4,6-11 are the drive circuits of the
LEDs on the operator panel. The LED lights when the signal is "H",
does not light when "L".

JAM cover open/closed

Operator Panel

AR-CF2  ELECTRICAL SECTION  9 - 9

This is the circuit of the operator panel board.

The operator panel drive board turns each of the LED1-6 on or off, and
detects weather each of the PSW1-3 is on or off.