Sharp AL-1611 (serv.man15) Service Manual ▷ View online
AL-1611/AL-1622
ELECTRICAL SECTION
13 – 5
C. IMAGE ASIC (HG73C039FD)
(1) Outline
The following figure shows the block diagram of the ASIC.
The ASIC is composed of the following three blocks; the image process section, the print control section, and the I/F section.
The image process section processes the image data from the CCD PWB according to the operation mode, such as shading, AE process, resolution
conversion and zooming.
conversion and zooming.
The print control section outputs the image-processed data during copying to the LSU (Laser unit) in synchronization with writing timing of the
LSU.The I/F section controls communication of interface (IEEE1284) with the host PC and controls DRAM of send/receive data buffer with the host
LSU.The I/F section controls communication of interface (IEEE1284) with the host PC and controls DRAM of send/receive data buffer with the host
PC. (Only for models with the printer function)
The ASIC is controlled by the CPU which writes the operation mode and the set values necessary for each operation mode to the ASIC control register.
112
DA1
DA1
OUT
Analog output 1
CCD reference
−
side
113
AVSS
POW
Analog ground pin
114
VSS
POW
Ground pin
115
TCLKD
LFTCLK
IN
Timer clock external input
Separator motor step count
Separator motor clock input
116
TIOCA2
TMCLK
OUT
Timer clock external output
Toner motor clock
960Hz clock output
117
TCLKC
SFTCLK
IN
Timer clock external input
Shifter motor step count
Shifter motor clock input
118
TIOCA1
PMCLK
OUT
Timer clock external output
Polygon motor clock
2078.74Hz clock output
119
TCLKB
SPFCLK
IN
Timer clock external input
SPF motor step count
SPF motor clock input
120
TCLKA
MIRCLK
IN
Timer clock external input
Mirror motor step count
Mirror motor clock input
121
/DACK1
OUT
DMAC channel 1 acknowl-
edge
edge
(Not used)
L: Acknowledge effective
122
/DACK0
OUT
DMAC channel 0 acknowl-
edge
edge
(Not used)
L: Acknowledge effective
123
MD0
IN
Operation mode setting pin
0
0
O p e r a t i o n m o d e s e t t i n g
(MODE 4)
(MODE 4)
Operation mode 4
124
MD1
IN
Operation mode setting pin
1
1
O p e r a t i o n m o d e s e t t i n g
(MODE 4)
(MODE 4)
Operation mode 4
125
MD2
IN
Operation mode setting pin
2
2
O p e r a t i o n m o d e s e t t i n g
(MODE 4)
(MODE 4)
Operation mode 4
126
PG0
RY/BY
IN
General port G0
Flash ROM busy signal
0: Busy state
127
/CS3
/CS3
OUT
Area 3 chip select
I/ O e x te n s i o n A S IC c h i p
select
select
L: Select effective
128
/CS2
/CS2
OUT
Area 2 chip select
Image ASIC chip select
L: Select effective
Pin No.
Pin name
Signal name
I/O
Function
Purpose
Descriptions
(Pin descriptions) IN: Input pin
OUT: Output pin
BIDIR: Bi-directional pin
ODN: Open drain output pin
TR1: 3-state output pin
POW: Power pin
Scan start
CCD
PWB
PWB
S
h
a
di
n
g
CCD
d
rive
AE
SRAM control
SRAM
32KB
x 2
32KB
x 2
Resolution conversion,
Zooming, lmage
process circuit
Zooming, lmage
process circuit
Print data process circuit
DRAM control
PRINT control
IEEE1284 control
DRAM
6MB or 4MB
6MB or 4MB
LSU
HSYNC
VSYNC
To CPU bus
TO PCI/F
PWB
PWB
ASIC
Image process section
I/F section
Print control section
ASIC control resistor
(Only for models
withthe printer
function)
withthe printer
function)
AL-1611/AL-1622
ELECTRICAL SECTION
13 – 6
(2) pin/signal table
PIN No.
Signal Name
IN/OUT
Description
1
/SCANSP
IN
Scanner process interrupt
signal
signal
2
/PRSTART
IN
Print start trigger signal
3
TMON
IN
Toner motor ON/OFF
4
TMCLK
IN
Toner motor reference clock
5
3.3V
Power
6
CPUAD7
IN
CPU address bus
7
CPUAD6
IN
8
GND
Power
9
CPUAD5
IN
CPU address bus
10
CPUAD4
IN
11
CPUAD3
IN
12
CPUAD2
IN
13
CPUAD1
IN
14
/CPUSYNC
OUT
Horizontal synchronization
signal
signal
15
/INTR
OUT
Interruption request signal
16
/CPUCS
IN
CPU chip select signal
17
/RESET
IN
Reset signal
18
5V
Power
19
GND
Power
20
3.3V
Power
21
GND
Power
22
MDATA15
IN/OUT
D ata b us o f D RA M (p a ge
memory)
memory)
23
MDATA14
IN/OUT
24
MDATA13
IN/OUT
25
MDATA12
IN/OUT
26
MDATA11
IN/OUT
27
MDATA10
IN/OUT
28
MDATA9
IN/OUT
29
MDATA8
IN/OUT
30
MDATA7
IN/OUT
31
3.3V
Power
32
MDATA6
IN/OUT
D ata b us o f D RA M (p a ge
memory)
memory)
33
MDATA5
IN/OUT
34
GND
Power
35
MDATA4
IN/OUT
D ata b us o f D RA M (p a ge
memory)
memory)
36
MDATA3
IN/OUT
37
MDATA2
IN/OUT
38
MDATA1
IN/OUT
39
MDATA0
IN/OUT
40
/RAS0
OUT
RAS signal 0 of DRAM (page
memory)
memory)
41
/RAS1
OUT
RAS signal 1 of DRAM (page
memory)
memory)
42
/RAS2
OUT
RAS signal 2 of DRAM (page
memory)
memory)
43
/RAS64
OUT
(Not used)
44
3.3V
Power
45
/RAS16
OUT
(Not used)
46
MAD0
OUT
Address bus of DRAM (page
memory)
memory)
47
GND
Power
48
MAD1
OUT
Address bus of DRAM (page
memory)
memory)
49
MAD2
OUT
50
MAD3
OUT
51
MAD4
OUT
52
MAD5
OUT
53
MAD6
OUT
54
MAD7
OUT
55
MAD8
OUT
56
MAD9
OUT
57
3.3V
Power
58
MAD10
OUT
Address bus of DRAM (page
memory)
memory)
59
MAD11
OUT
60
GND
Power
61
/CAS0
OUT
CAS signal of DRAM (page
memory)
memory)
62
/CAS1
OUT
63
/OE
OUT
Read enable signal of DRAM
(page memory)
(page memory)
64
/WE
OUT
Write enable signal of DRAM
(page memory)
(page memory)
65
OUTD0
OUT
(Not used)
66
OUTD1
OUT
67
OUTD2
OUT
68
OUTD3
OUT
69
3.3V
Power
70
OUTD4
OUT
(Not used)
71
OUTD5
OUT
72
GND
Power
73
OUTD6
OUT
(Not used)
74
OUTD7
OUT
75
OUTD8
OUT
76
OUTD9
OUT
77
OUTD11
OUT
78
OUTD10
OUT
79
OUTD12
OUT
80
OUTD13
OUT
81
OUTD14
OUT
82
OUTD15
OUT
83
/HSYNC
OUT
84
/PCLPRD
IN
85
/PCLREQ
OUT
86
/PCLACK
IN
87
/PCLCS
IN
88
3.3V
Power
89
GND
Power
90
5V
Power
91
GND
Power
92
/FAXPRD
IN
(Not used)
PIN No.
Signal Name
IN/OUT
Description
AL-1611/AL-1622
ELECTRICAL SECTION
13 – 7
93
/FAXREQ
OUT
(Not used)
94
/FAXACK
IN
95
3.3V
Power
96
/FAXCS
IN
(Not used)
97
/ESPRD
IN
98
GND
Power
99
/ESREQ
OUT
(Not used)
100
/ESACK
IN
101
/ESCS
IN
102
PARAD0
IN/OUT
103
PARAD1
IN/OUT
104
PARAD2
IN/OUT
105
PARAD3
IN/OUT
106
PARAD4
IN/OUT
107
PARAD5
IN/OUT
108
5V
Power
109
PARAD6
IN/OUT
(Not used)
110
PARAD7
IN/OUT
111
GND
Power
112
/REV
OUT
(Not used)
113
INIT
IN
114
/SLCTIN
IN
115
/AUTOFD
IN
116
/STB
IN
117
/ACK
OUT
118
BUSY
OUT
119
PE
OUT
120
/FAULT
OUT
121
5V
Power
122
SLCT
OUT
(Not used)
123
/TESTPIN0
IN
High: Normal Low: Test
124
GND
Power
125
PFCLK
IN
Write clock
126
/TESTPIN1
IN
High: Normal Low: Test
127
/SYNCEN
OUT
Jitter adjustment IC trigger
signal
signal
128
SD10
IN/OUT
Data line to SRAM before are
separation
separation
129
SD11
IN/OUT
130
SD12
IN/OUT
131
SD13
IN/OUT
132
SD14
IN/OUT
133
5V
Power
134
SD15
IN/OUT
Data line to SRAM before are
separation
separation
135
SD16
IN/OUT
136
GND
Power
137
SD17
IN/OUT
Data line to SRAM before are
separation
separation
138
SOE1
OUT
Read enable line to SRAM
before area separation
before area separation
139
SWE1
OUT
Write enable line to SRAM
before area separation
before area separation
PIN No.
Signal Name
IN/OUT
Description
140
SCS1
OUT
Chip select lin e to SRAM
before area separation
before area separation
141
SOE0
OUT
Read enable line to SRAM
before area separation
before area separation
142
SWE0
OUT
Write enable line to SRAM
before area separation
before area separation
143
SCS0
OUT
Chip select lin e to SRAM
before area separation
before area separation
144
SD00
IN/OUT
Data line to SRAM before are
separation
separation
145
SD01
IN/OUT
146
5V
Power
147
SD02
IN/OUT
Data line to SRAM before are
separation
separation
148
SD03
IN/OUT
149
GND
Power
150
SD04
IN/OUT
Data line to SRAM before are
separation
separation
151
SD05
IN/OUT
152
SD06
IN/OUT
153
SD07
IN/OUT
154
SAD0
OUT
Address line to SRAM before
area separation
area separation
155
SAD1
OUT
156
SAD2
OUT
157
SAD3
OUT
158
SAD4
OUT
159
SAD5
OUT
160
SAD6
OUT
161
SAD7
OUT
162
GND
Power
163
SAD8
OUT
Address line to SRAM before
area separation
area separation
164
SAD9
OUT
165
SAD10
OUT
166
SAD11
OUT
167
SAD12
OUT
168
SAD13
OUT
169
/f1
OUT
CCD drive signal transfer
clock (First phase)
clock (First phase)
170
/f2
OUT
CCD drive signal transfer
clock (Second phase)
clock (Second phase)
171
/SH
OUT
CCD drive signal shift pulse
172
5V
Power
173
RS
OUT
CCD drive signal reset pulse
174
SP
OUT
CCD drive signal sampling
hold pulse
hold pulse
175
GND
Power
176
CP
OUT
A/D conversion IC latch clock
177
BCLK
OUT
CCD shield output latch sig-
nal
nal
178
IDIN0
IN
Image scan data (after 8bit A/
D conversion)
D conversion)
179
IDIN1
IN
180
IDIN2
IN
181
IDIN3
IN
182
IDIN4
IN
183
IDIN5
IN
184
IDIN6
IN
PIN No.
Signal Name
IN/OUT
Description
AL-1611/AL-1622
ELECTRICAL SECTION
13 – 8
185
5V
Power
186
IDIN7
IN
Image scan data (after 8bit A/
D conversion)
D conversion)
187
/SDCLK
OUT
Effective image area signal
188
GND
Power
189
SFCLK
IN
CCD drive clock (48MHz)
190
TEST port 0
IN
High: Normal Low: Test
191
/SYNC
IN
Horizontal synchronization
signal (HSYNC) from LSU
signal (HSYNC) from LSU
192
/LD
OUT
Laser drive signal
193
/LEND
OUT
Laser APC signal
194
/VIDEOCS
OUT
Video data control
195
OUT
NC
196
OUT
197
3.3V
Power
198
OUT
NC
199
OUT
200
GND
Power
201
OUT
NC
202
OUT
203
OUT
204
OUT
205
OUT
206
OUT
207
OUT
208
OUT
209
OUT
210
3.3V
Power
211
OUT
NC
212
OUT
213
GND
Power
214
/PCLPCS
OUT
PCL option print data control
215
/FAXPCS
OUT
FAX option print data control
216
/ESPCS
OUT
Electronic sort option print
data control
data control
217
OUT
NC
218
CV_START
OUT
Copy vendor control
219
CV_COUNT
OUT
220
CV_SIZE3
OUT
221
CV_SIZE2
OUT
222
CV_SIZE1
OUT
223
5V
Power
224
CV_SIZE0
OUT
Copy vendor control
225
CV_DPX
OUT
226
GND
Power
227
CV_CA
OUT
Copy vendor control
228
OUT
NC
229
TM
OUT
Toner motor drive output (+)
230
TM_
OUT
Toner motor drive output (
−
)
231
CPUD15
IN/OUT
CPU data bus
PIN No.
Signal Name
IN/OUT
Description
232
CPUD14
IN/OUT
CPU data bus
233
CPUD13
IN/OUT
234
CPUD12
IN/OUT
235
CPUD11
IN/OUT
236
5V
Power
237
CPUD10
IN/OUT
CPU data bus
238
CPUD9
IN/OUT
239
GND
Power
240
CPUD8
IN/OUT
CPU data bus
241
CPUD7
IN/OUT
242
CPUD6
IN/OUT
243
CPUD5
IN/OUT
244
CPUD4
IN/OUT
245
CPUD3
IN/OUT
246
CPUD2
IN/OUT
247
CPUD1
IN/OUT
248
CPUD0
IN/OUT
249
3.3V
Power
250
/CPUWR
IN
CPU write signal
251
/CPURD
IN
CPU read signal
252
GND
Power
253
CPUCLK
IN
CPU system clock
254
GND
Power
255
TEST PORT1
IN
High: Normal Low: Test
256
/SCANST
IN
Scanner process start signal
PIN No.
Signal Name
IN/OUT
Description
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