Sharp UP-3500 (serv.man29) Service Manual ▷ View online
UP-3500 (V)
CIRCUIT DIAGRAM
– 47 –
EFTC#
RS3_DTR#
RS3_SIN
RS3_CTS#
RS3_RTS#
RS3_RI#
RS3_DCD#
RS3_DSR#
RS3_SOUT
RS4_CTS#
RS4_SOUT
RS4_DCD#
RS4_SIN
RS4_DTR#
RS4_DSR#
RS4_RTS#
RS4_RI#
FPGA_DSR4
FPGA_CTS4
FPGA_SIN4
FPGA_RI4
FPGA_DCD4
EFT_RTS#
EFT_DTR#
EFT_SOUT
FPGA_SOUT4
FPGA_DTR4
FPGA_RTS4
EFT_CTS#
EFT_SIN
EFT_DSR#
EFT_RI#
EFT_DCD#
FPGA_RI3
FPGA_SIN3
FPGA_SOUT3
FPGA_CTS3
FPGA_RTS3
FPGA_DTR3
FPGA_DSR3
FPGA_DCD3
5V
3.3V
EFTC#
EFT_VCC
5V_2
3
2
3.3V
3.3V
3.3V
3.3V
5V
EFT_VCC
3.3V
3.3V
3.3V
GND-FRAME
GND-FRAME
GND-FRAME
GND-FRAME
C131
100pF
C130
100pF
R235
33
C133
0.1uF
R404
(0)
R232
33
IC16
ICL3241ECA-1
28
24
1
2
14
13
12
21
19
18
17
16
15
23
25
26
27
3
9
10
11
20
4
5
6
7
8
22
C1+
C1-
C2+
C2-
T1in
T2in
T3in
R1outB
R1out
R2out
R3out
R4out
R5out
EN#
GND
VCC
V+
V-
T1out
T2out
T3out
R2outB
R1in
R2in
R3in
R4in
R5in
SHDN#
R244
0
C140
100pF
R238
33
+
C123
10uF/50V
1
2
C124
0.1uF
CN13
RS232C CN(D-SUB 9Pin)
1
2
3
4
5
6
7
8
9
10
11
1
2
3
4
5
6
7
8
9
10
11
C127
0.1uF
C122
0.1uF
R246
10K
C142
100pF
R248
10K
R405
(0)
+
C134
10uF/50V
1
2
CN23
RS232C CN(D-SUB 9Pin)
1
2
3
4
5
6
7
8
9
10
11
1
2
3
4
5
6
7
8
9
10
11
C135
0.1uF
R247
0
R395
0 (3216)
1
2
R406
(0)
C128
100pF
R237
33
C132
100pF
R233
33
C129
100pF
R250
0
IC17
ICL3241ECA-1
28
24
1
2
14
13
12
21
19
18
17
16
15
23
25
26
27
3
9
10
11
20
4
5
6
7
8
22
C1+
C1-
C2+
C2-
T1in
T2in
T3in
R1outB
R1out
R2out
R3out
R4out
R5out
EN#
GND
VCC
V+
V-
T1out
T2out
T3out
R2outB
R1in
R2in
R3in
R4in
R5in
SHDN#
IC18
SN74LV157AP
W
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SELECT
1A
1B
1Y
2A
2B
2Y
GND
3Y
3B
3A
4Y
4B
4A
STROBE
VCC
C141
100pF
R234
33
R429
0 (3216)
1
2
R421
0 (3216)
1
2
R240
33
C139
100pF
C136
0.1uF
SP1
5
SHORT PIN & SOCKET
1
3
2
R428
0 (3216)
1
2
R413
0
R251
47
K
R249
0
R241
33
C126
0.1uF
C125
0.1uF
C143
100pF
R243
0
C137
0.1uF
R239
33
R242
0
R245
10
K
R236
33
C138
0.1uF
RS232 ch3-4
<RS232 ch3>
FPGA
FPGA
Intersil ICL 3241
<RS232 ch4>
MODIFIED 08,03,27
MODIFIED 08,03,27
modified 07,06,09
MODIFIED 08,03,27
MODIFIED 08,03,27
MODIFIED 08,03,27
MODIFIED 08,03,27
Intersil ICL 3241
1-2 short: 5V (default)
2-3 short: RI#
MODIFIED 07,10,12
MODIFIED 07,10,12
MODIFIED 07,10,12
MODIFIED 07,10,12
A
B
C
D
876
5
4
3
21
1
2
3
4
5
6
7
8
D
C
B
A
A
B
C
D
876
5
4
3
21
1
2
3
4
5
6
7
8
D
C
B
A
A
B
C
D
876
5
4
3
21
1
2
3
4
5
6
7
8
D
C
B
A
A
B
C
D
876
5
4
3
21
1
2
3
4
5
6
7
8
D
C
B
A
9/16
RS232C DRIVER (CH3-CH-4)
UP-3500 (V)
CIRCUIT DIAGRAM
– 48 –
RS232 ch5(for 20DP)
Intersil ICL 3241
<RS232 ch5>
for 20DP
For P20DP(External Display)
FPGA
For I20DP(Internal Display)
Intersil ICL 3241
<RS232 ch6>
FPGA
SP5 , SP6 : CN9 signal
-------------------------
1-2 , NU : 5V
2-3 , NU : GND
NU , 1-2 : CD (default)
NU , 2-3 : RI
modified 07,06,09
(Install to Not Install)
MODIFIED 07,10,12
MODIFIED 07,10,12
MODIFIED 07,10,12
RTS5
DCD5
RI5
CTS5
SIN5
DSR5
RS5_DTR#
RS5_SOUT
RS5_DSR#
RS6_SIN
RS6_DTR#
RS6_RTS#
RS6_DTR#
RS6_RTS#
RS6_RI#
RS6_CTS#
RS6_DSR#
RS6_SOUT
RS6_DCD#
RS6_DSR#
RS6_DCD#
RS6_RI#
RS6_SOUT
RS6_SIN
RS6_CTS#
FPGA_DSR5
FPGA_DCD5
FPGA_CTS5
FPGA_DTR5
FPGA_SIN5
FPGA_SOUT5
FPGA_RI5
FPGA_RTS5
3.3V
5V
FPGA_DCD6
FPGA_RTS6
FPGA_DSR6
FPGA_CTS6
FPGA_RI6
FPGA_SOUT6
FPGA_SIN6
FPGA_DTR6
5V_2
3
2
3.3V
3.3V
3.3V
5V
GND-FRAME
GND-FRAME
3.3V
3.3V
3.3V
GND-FRAME
GND-FRAME
R425
0 (3216)
1
2
IC19
ICL3241ECA-1
28
24
1
2
14
13
12
21
19
18
17
16
15
23
25
26
27
3
9
10
11
20
4
5
6
7
8
22
C1+
C1-
C2+
C2-
T1in
T2in
T3in
R1outB
R1out
R2out
R3out
R4out
R5out
EN#
GND
VCC
V+
V-
T1out
T2out
T3out
R2outB
R1in
R2in
R3in
R4in
R5in
SHDN#
C266
0.1uF
J5
RJ45
1
2
3
4
5
6
7
8
9
10
CN9
RJ45 MODULAR 3017S-8811
1
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6
7
8
FGND
FGND
FB6
CIB32P600NE
R256
10K
C268
100pF
F2
T1A/25
0
V
SP6
SHORT PIN & SOCKET
1
3
2
C148
0.1uF
+
C262
10uF/50V
1
2
R255
10
K
IC44
ICL3241ECA-1
28
24
1
2
14
13
12
21
19
18
17
16
15
23
25
26
27
3
9
10
11
20
4
5
6
7
8
22
C1+
C1-
C2+
C2-
T1in
T2in
T3in
R1outB
R1out
R2out
R3out
R4out
R5out
EN#
GND
VCC
V+
V-
T1out
T2out
T3out
R2outB
R1in
R2in
R3in
R4in
R5in
SHDN#
R401
33
C270
100pF
C144
0.1uF
+
C145
10uF/50V
1
2
C265
0.1uF
jamper
JP1
1
2
--
R402
33
J3
53015
-0710
1
2
3
4
5
6
7
C267
100pF
C149
0.1uF
C150
1000pF
C146
0.1uF
R430
0 (3216)
1
2
C271
100pF
R403
33
TP
1
1
C147
0.1uF
C263
0.1uF
R399
33
C261
0.1uF
SP5
SHORT PIN & SOCKET
1
3
2
R253
10K
R400
33
R252
10
0
R220
(0)
R254
10
K
C264
0.1uF
C269
100pF
A
B
C
D
876
54
3
21
1
2
3
4
5
6
7
8
D
C
B
A
A
B
C
D
876
54
3
21
1
2
3
4
5
6
7
8
D
C
B
A
A
B
C
D
876
54
3
21
1
2
3
4
5
6
7
8
D
C
B
A
A
B
C
D
876
54
3
21
1
2
3
4
5
6
7
8
D
C
B
A
10/16
RS232C DRIVER (CH5-CH-6)
UP-3500 (V)
CIRCUIT DIAGRAM
– 49 –
㪤㪚㪩㩷㪠
㪆㪝
FPGA
modified 07,06,09
NOT M
ount
---------------------------
1-2 : by software(default)
2-3 : always ON(used when Flash does not have FPGA CONFIG data.)
MCR_RDD2#
MCR_RCP2#
MCR_RDD1#
MCR_RCP3#
MCR_RCP1#
MCR_CLS2#
MCR_RDD3#
MCR_CLS3#
MCR_CLS1#
MCR_CLS2#
MCR_RCP1#
MCR_RCP3#
INV_VADJ
MCR_CLS1#
MCR_RDD1#
MCR_RDD2#
MCR_RCP2#
MCR_CLS3#
MCR_RDD3#
INVPON
FPGA_CLS1#
FPGA_RDD2#
FPGA_RDD1#
FPGA_RCP2#
FPGA_RCP1#
FPGA_RDD3#
FPGA_CLS3#
FPGA_CLS2#
5V
FPGA_RCP3#
3.3V
LED_PWR
INV_VADJ
5V
INVPON
5V
3.3V
3.3V
3.3V
5V
INVGND
5V
3.3V
C156 100PF
2
1
C259
0.1uF
C158 100PF
2
1
C155 100PF
2
1
F10
T2.0A/250V
C260
0.1uF
C272
0.1uF
C183
0.1uF
C160 100PF
2
1
C157 100PF
2
1
F11
T2.0A/250V
IC27C
74LV0
8
A
P
W
9
10
8
SP1
6
(SHORT PIN & SOCKET)
1
3
2
J14
BM30B-SRDS-G-TF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
IC38A
74LV0
8
A
P
W
1
2
3
14
7
C159 100PF
2
1
C152 100PF
2
1
IC39A
74LV0
8
A
P
W
1
2
3
14
7
BR6
33-
4
1
8
2
7
3
6
4
5
IC27B
74LV08
A
P
W
4
5
6
C153 100PF
2
1
R417
10
0
BR3
10K
-4
1
8
2
7
3
6
4
5
FB9
CIB32P600NE
IC38D
74LV0
8
A
P
W
12
13
11
C154 100PF
2
1
R391
200
BR7
33-
4
1
8
2
7
3
6
4
5
IC27D
74LV0
8
A
P
W
12
13
11
IC39D
74LV0
8
A
P
W
12
13
11
FB8
CIB32P600NE
IC38C
74LV0
8
A
P
W
9
10
8
BR8
33-
4
1
8
2
7
3
6
4
5
BR4
10K-
4
1
8
2
7
3
6
4
5
IC39C
74LV0
8
A
P
W
9
10
8
BR5
10K-
4
1
8
2
7
3
6
4
5
IC38B
74LV08
A
P
W
4
5
6
C151
0.1uF
IC39B
74LV0
8
A
P
W
4
5
6
IC27A
74LV0
8
A
P
W
1
2
3
14
7
A
B
C
D
876
5
4
3
21
1
2
3
4
5
6
7
8
D
C
B
A
A
B
C
D
876
5
4
3
21
1
2
3
4
5
6
7
8
D
C
B
A
A
B
C
D
876
5
4
3
21
1
2
3
4
5
6
7
8
D
C
B
A
A
B
C
D
876
5
4
3
21
1
2
3
4
5
6
7
8
D
C
B
A
11/16
MCR.I/F
UP-3500 (V)
CIRCUIT DIAGRAM
– 50 –
DRW1#
DRW2#
DRSNS
DRAWER1
DRWSNS
3
DRAWER2
FPGA_DRWSNS
3
19V
PGND
19V
F3
500mA/250V
CN15
22-05-1032(5046-03A
)
DRAWER CN1
1
2
3
R261
4.7K
D6
1SS355
1
2
D4
1SS355
1
2
R258
1.8K
R264
1.8K
FB7
CIB32P600NE
+
C163
22uF/16V
R260
330
R259
30K
R257
100
+
C161
22uF/16V
CN16
22-05-1032(5046-03A
)
DRAWER CN2
1
2
3
R263
100
C162
1000pF
Q20
2SD2143
Q19
2SD2143
D3
VHD1SR159//-1(1SR159-200)
1
2
R262
(10K)
D5
1SR159-200
1
2
<DRAWER>
FGPA
FGPA
A
B
C
D
876
54
3
21
1
2
3
4
5
6
7
8
D
C
B
A
A
B
C
D
876
54
3
21
1
2
3
4
5
6
7
8
D
C
B
A
A
B
C
D
876
54
3
21
1
2
3
4
5
6
7
8
D
C
B
A
A
B
C
D
876
54
3
21
1
2
3
4
5
6
7
8
D
C
B
A
12/16
DRA
WER
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