Sharp ER-A880 (serv.man3) Service Manual ▷ View online
Pin
Number
Pin Symbol
Pin
Type
Description
1
MR
I
Master Reset. When high,
this input clears all registers,
except the parallel port data
and status registers (UART
receiver buffer, transmitter
holding, divisor latch
registers). In the flexible disk
controller, it resets all disk
drive output lines to their
disabled state. Reset clears
the drive control register, sets
the data rate register to 250
kb/s, and sets the main status
register to 80. The mode
register default values are
given in the mode register
description. To prevent
glitches from activating the
reset sequence, attach a
1000 pF capacitor to this pin.
this input clears all registers,
except the parallel port data
and status registers (UART
receiver buffer, transmitter
holding, divisor latch
registers). In the flexible disk
controller, it resets all disk
drive output lines to their
disabled state. Reset clears
the drive control register, sets
the data rate register to 250
kb/s, and sets the main status
register to 80. The mode
register default values are
given in the mode register
description. To prevent
glitches from activating the
reset sequence, attach a
1000 pF capacitor to this pin.
95, 94
MTR0,
MTR1
MTR1
O
Motors. These high drive
open drain outputs are motor
enable signals for drives 0
and 1. These pins contain
encoded drive select
information if bit 7 of the
configuration register is set.
Otherwise they are controlled
through bits in the drive
control register.
open drain outputs are motor
enable signals for drives 0
and 1. These pins contain
encoded drive select
information if bit 7 of the
configuration register is set.
Otherwise they are controlled
through bits in the drive
control register.
76
OSC1
I
Oscillator. One side of an
external 24 MHz crystal is
attached here. This pin is tied
low if an external clock is
used.
external 24 MHz crystal is
attached here. This pin is tied
low if an external clock is
used.
75
OSC2/CLK
I/O
Oscillator Clock. One side of
an external 24 MHz crystal is
attached here. If a crystal is
not used, a TTL or CMOS
compatible clock is connected
to this pin.
an external 24 MHz crystal is
attached here. If a crystal is
not used, a TTL or CMOS
compatible clock is connected
to this pin.
26
∼
19
PD0
∼
PD7
O
Port Data. These bidirectional
pins transfer data to and from
the peripheral data bus.
These pins have high current
drive capability.
pins transfer data to and from
the peripheral data bus.
These pins have high current
drive capability.
30
PE
I
Paper End. This input is set
high by the printer when it is
out of paper.
high by the printer when it is
out of paper.
38
POE
I
Port Output Enable. When
low, data written to the
parallel port data register is
output through PD0
low, data written to the
parallel port data register is
output through PD0
∼
PD7.
When high, PD0
∼
PD7 are in
a high impedance state and
act as inputs. This pin is
usually tied low for printer
operation.
act as inputs. This pin is
usually tied low for printer
operation.
83
PUMP/
PREN
PREN
I/O
Pump/Precompensation
Enable. When the PU bit is
set in mode command, this
pin is an output that indicates
when the charge pump is
making a correction.
Otherwise this pin is an input
that sets the precomp mode
(Table 11). If pin is configured
as PUMP, PREN is assumed
high.
Enable. When the PU bit is
set in mode command, this
pin is an output that indicates
when the charge pump is
making a correction.
Otherwise this pin is an input
that sets the precomp mode
(Table 11). If pin is configured
as PUMP, PREN is assumed
high.
Pin
Number
Pin Symbol
Pin
Type
Description
15
RD
I
Read. When this input is low
while the chip is selected, the
CPU can read status
information or data from the
selected register.
while the chip is selected, the
CPU can read status
information or data from the
selected register.
78
RDATA
I
Read Data. The active low
raw data read from the disk is
connected here.
raw data read from the disk is
connected here.
50, 49
RI1, RI2
I
Ring Indicator. When low,
this input indicates that a
telephone ringing signal has
been received by the modem
or data set. RI is a modem
status input whose condition
can be tested by the CPU
through reading bit 6 (RI) of
the MSR. Bit 6 is the
complement of RI. Bit 2
(TERI) of the MSR shows
whether RI has changed state
since the previous reading of
the MSR. Whenever the RI bit
of the MSR changes from a
high to a low state, an
interrupt is generated if the
modem status interrupt is
enabled.
this input indicates that a
telephone ringing signal has
been received by the modem
or data set. RI is a modem
status input whose condition
can be tested by the CPU
through reading bit 6 (RI) of
the MSR. Bit 6 is the
complement of RI. Bit 2
(TERI) of the MSR shows
whether RI has changed state
since the previous reading of
the MSR. Whenever the RI bit
of the MSR changes from a
high to a low state, an
interrupt is generated if the
modem status interrupt is
enabled.
88
RPM/LC
O
Revolution Per Minute/Low
Current. This high drive open
drain output pin has two
functions based on the
selection of the DRVTYP pin:
(1) When using a dual-speed
spindle motor flexible drive
(DRVTYP pin low), this output
is used to set the spindle
motor speed to either 300
RPM or 360 RPM. In this
mode, this output goes low
when 250/300 kb/s data rate
is chosen in the data rate
register, and high when 500
kb/s is chosen. (2) When
using a single-speed spindle
motor flexible drive (DRVTYP
pin high), this pin indicates
when to reduce the write
current to the drive. This
output is high for high density
media (when 500 kb/s is
chosen).
Current. This high drive open
drain output pin has two
functions based on the
selection of the DRVTYP pin:
(1) When using a dual-speed
spindle motor flexible drive
(DRVTYP pin low), this output
is used to set the spindle
motor speed to either 300
RPM or 360 RPM. In this
mode, this output goes low
when 250/300 kb/s data rate
is chosen in the data rate
register, and high when 500
kb/s is chosen. (2) When
using a single-speed spindle
motor flexible drive (DRVTYP
pin high), this pin indicates
when to reduce the write
current to the drive. This
output is high for high density
media (when 500 kb/s is
chosen).
55, 43
RTS1,
RTS2
RTS2
O
Request to Send. When low,
this output indicates to the
modem or data set that the
UART is ready to exchange
data. RTS can be set to an
active low by programming bit
1 (RTS) of the MCR. A
master reset operation sets
this signal to its inactive (high)
state. If XTSEL is high during
reset, loop mode operation
holds this signal in its inactive
state. If low, MCR bit 1
controls the associated pin
during loop mode operation.
this output indicates to the
modem or data set that the
UART is ready to exchange
data. RTS can be set to an
active low by programming bit
1 (RTS) of the MCR. A
master reset operation sets
this signal to its inactive (high)
state. If XTSEL is high during
reset, loop mode operation
holds this signal in its inactive
state. If low, MCR bit 1
controls the associated pin
during loop mode operation.
– 8 –
Pin
Number
Pin Symbol
Pin
Type
Description
85
SETCUR
O
Set Current. An external
resistor connected from this
pin to analog ground
programs the amount of
charge pump current that
drives the external filters. This
PLL Filter Design section
shows how to determine the
values.
resistor connected from this
pin to analog ground
programs the amount of
charge pump current that
drives the external filters. This
PLL Filter Design section
shows how to determine the
values.
56, 42
SIN1, SIN2
I
Serial Input. This input
receives composite serial
data from the
communications link
(peripheral device, modem, or
data set).
receives composite serial
data from the
communications link
(peripheral device, modem, or
data set).
29
SLCT
I
Select. This input is set high
by the printer when the printer
is selected.
by the printer when the printer
is selected.
37
SLIN
O
Select Input. This output
selects the printer when the
signal is low.
selects the printer when the
signal is low.
57, 41
SOUT1,
SOUT2
SOUT2
O
Serial Output. This output
sends composite serial data
output to the communications
link (peripheral, modem or
data set). The SOUT signal is
set to the marking (logic 1)
state upon a master reset
operation.
sends composite serial data
output to the communications
link (peripheral, modem or
data set). The SOUT signal is
set to the marking (logic 1)
state upon a master reset
operation.
33
STB
O
Data Strobe. This output
indicates to the peripheral that
data at the parallel port is
valid.
indicates to the peripheral that
data at the parallel port is
valid.
87
STEP
O
Step. This open drain high
drive output produces a pulse
at a software programmable
rate to move the head during
a seek operation.
drive output produces a pulse
at a software programmable
rate to move the head during
a seek operation.
71
TC
I
Terminal Count. This active
high input indicates the end of
a DMA transfer. This signal is
enabled when the DMA
acknowledge pin is active.
high input indicates the end of
a DMA transfer. This signal is
enabled when the DMA
acknowledge pin is active.
97
TRK0
I
Track 0. This active low input
tells the controller that the
head is at track zero of the
selected disk drive.
tells the controller that the
head is at track zero of the
selected disk drive.
81, 74,
45, 34
45, 34
VDD, A, B,
C, D
C, D
+5V Power. This is the power
supplied to the FDC analog,
FDC digital, serial ports, and
parallel port circuitry,
respectively.
supplied to the FDC analog,
FDC digital, serial ports, and
parallel port circuitry,
respectively.
77, 100,
65, 59,
27, 89
65, 59,
27, 89
VSS A, B, C,
D, E, F
D, E, F
0V Reference. This is the
reference voltage for the
FDC, analog, FDC digital,
CPU interface, serial ports,
parallel port, and disk
interface output drive circuitry,
respectively.
reference voltage for the
FDC, analog, FDC digital,
CPU interface, serial ports,
parallel port, and disk
interface output drive circuitry,
respectively.
90
WDATA
O
Write Data. This high drive
open drain output is a write
pre-compensated serial data
to be written onto the selected
disk drive.
open drain output is a write
pre-compensated serial data
to be written onto the selected
disk drive.
Pin
Number
Pin Symbol
Pin
Type
Description
86
WGATE
O
Write Gate. This active low
open drain high drive output
enables the write circuitry of
the selected disk drive. This
signal has been designed to
prevent glitches during power
up and power down. This
prevents writing to the disk
when power is cycled.
open drain high drive output
enables the write circuitry of
the selected disk drive. This
signal has been designed to
prevent glitches during power
up and power down. This
prevents writing to the disk
when power is cycled.
99
WPROT
I
Write Protect. This input
indicates that the disk is write
protected. When a disk is
write protected, any
command that writes to it is
inhibited.
indicates that the disk is write
protected. When a disk is
write protected, any
command that writes to it is
inhibited.
14
WR
I
Write. When this input is low
while the chip is selected,
CPU can write control words
or data into the selected
register.
while the chip is selected,
CPU can write control words
or data into the selected
register.
18
XTSEL
I
XT Select. When this input is
low during reset, the chip
operates in the XT compatible
mode. When high, it operates
in the AT compatible mode. A
pull down or pull up resistor
must always be attached to
this pin.
low during reset, the chip
operates in the XT compatible
mode. When high, it operates
in the AT compatible mode. A
pull down or pull up resistor
must always be attached to
this pin.
FUNCTIONAL DESCRIPTION
The following sections describe each of the M5105 major functional
blocks. Each functional block is described as independently of the
other blocks as possible. Software can address all blocks inde-
pendently of each other,, except for the configuration register and low
power mode operation. The configuration register affects all other
blocks by determining which ones the address decoder can activate.
The low power mode is enabled and disabled via the flexible disk
controller mode command. Enabling low power mode stops the 24
MHz crystal and clock oscillation to all logic blocks. Software should
ensure that both UARTs and the flexible disk controller are idle and
continue to be idle while the low power mode is enabled.
blocks. Each functional block is described as independently of the
other blocks as possible. Software can address all blocks inde-
pendently of each other,, except for the configuration register and low
power mode operation. The configuration register affects all other
blocks by determining which ones the address decoder can activate.
The low power mode is enabled and disabled via the flexible disk
controller mode command. Enabling low power mode stops the 24
MHz crystal and clock oscillation to all logic blocks. Software should
ensure that both UARTs and the flexible disk controller are idle and
continue to be idle while the low power mode is enabled.
1. ADDRESS DECODER
This decodes address signals A0
∼
A9 and qualifies them. If qualified,
it activates the appropriate function block. The XTSEL pin determines
whether function blocks respond to the industry standard XT or AT
address.
whether function blocks respond to the industry standard XT or AT
address.
– 9 –
4. Jumper pin setting
1) J1, J2
Jumper
No.
Description
RI
+5V
J1
Used to set
RS CN1 9pin
signal.
RS CN1 9pin
signal.
RI signal
(input) initial
setting
+5V (output)
J2
Used to set
RS CN1 9pin
signal.
RS CN1 9pin
signal.
RI signal
(input) initial
setting
+5V (output)
2) J3, J4
Jumper No.
Description
J4
J3
1
1
Sets PR CN1 to LPT1. (378h
∼
17Fh)
Initial
setting
setting
1
0
Sets PR CN1 to LPT3. (378h
∼
37Fh)
0
1
Sets PR CN1 to LPT32 (378h
∼
37Fh)
0
0
PR CN1 disabled
3) J5, J6, J7
Jumper No.
Description
J7
J6
J5
RS CN1
RS CN2
1
1
1
COM1
(3F8h
(3F8h
∼
3FFh)
[COM3]
(3E8h
(3E8h
∼
3EFh)
COM2
(2F8h
(2F8h
∼
2FFh)
[COM4]
(2E8h
(2E8h
∼
2EFh)
Initial
setting
setting
1
1
0
DISABLED
COM2 [COM4]
1
0
1
COM1 [COM3]
DISABLED
1
0
0
DISABLED
DISABLED
0
1
1
COM2 [COM4]
COM1 [COM3]
0
1
0
DISABLED
COM1 [COM3]
0
0
1
COM2 [COM4]
DISABLED
0
0
0
DISABLED
DISABLED
*
When J9 is set to LOW, settings are shown in [ ].
4) J8
Jumper No.
Description
J8
Reserved: Fixed to 0.
5) J9
Jumper
No.
Description
H
L
J9
Sets RS CN.
COM1,
COM2 are
used.
COM3,
COM4 are
used.
Initial setting
6) J10
Jumper
No.
Description
5
7
J10
Sets the parallel port
interruption level.
interruption level.
IRQ5 is
used.
IRQ7 is
used.
7) J11
∼
J17
Jumper
No.
Description
1
2
J17
Sets the
RS232 port
interruption
level.
RS232 port
interruption
level.
COM1
[COM3] uses
IRQ3.
COM2
[COM4] uses
IRQ3.
J16
COM1
[COM3] uses
IRQ4.
COM2
[COM4] uses
IRQ4.
J15
COM1
[COM3] uses
IRQ9.
COM2
[COM4] uses
IRQ9.
Initial
setting
of 1
setting
of 1
J14
COM1
[COM3] uses
IRQ10.
COM2
[COM4] uses
IRQ10.
Initial
setting
of 2
setting
of 2
J13
COM1
[COM3] uses
IRQ11.
COM2
[COM4] uses
IRQ11.
J12
COM1
[COM3] uses
IRQ12.
COM2
[COM4] uses
IRQ12.
J11
COM1
[COM3] uses
IRQ15.
COM2
[COM4] uses
IRQ15.
8) J15
Jumper
No.
Description
O
I
J18
Parallel port
data setting
data setting
Set to output.
Initial setting
Set to input.
J1
RI +5V
J2
RI
+
5
V
J3
J4
J5
J6
J7
J8
01
J9
L
H
J10
5 7
J1
8
0
I
J1
1
J1
2
J1
3
J1
4
J1
5
J1
6
J1
7
21
Jumper pin layout
RI +5V
– 10 –
ER-
A
8RS CIRCUIT
DIAG
RAM
SU
P
PER
I
/O
C
H
IP
1/
5
VC
C
C
109
0.
1
u
FB
1
RD3
5
C
C
120
0.
1
u
C1
2
4
0.
1
u
C1
1
0u/
1
0
V
O
S
S
D
[0
..7
]
R1
2
0
15
0
R1
0
3
2K
R
104
2K
R1
0
1
150
R1
0
2
15
0
R1
0
0
15
0
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
VCC
R
106
10
K
R1
1
0
15
0
A9
2
A8
3
A7
4
A6
5
A5
6
A4
7
A3
8
A2
9
A1
10
A0
11
AE
N
12
IO
L
13
IO
W
14
IO
R
15
RESE
T
1
IR
Q
R
2
58
IR
Q
R
1
40
IR
Q
F
D
72
IR
Q
P
39
DRQ
69
DAK
70
TC
71
SIN1
56
SOUT
1
/CRB7
57
CT
S1
51
DSR1
53
DT
R1
/CRB3
54
RT
S1
/CR
B
4
55
RI
1
50
DCD
1
52
SIN2
42
SOUT
2
/CRB0
41
CT
R2
48
DSR2
46
RI
2
49
DT
R2
/CRB2
44
RT
S2
/CR
B
1
43
DCD
2
47
DP7
19
DP6
20
DP5
21
DP4
22
DP3
23
DP2
24
DP1
25
DP0
26
D0
60
D1
61
D2
62
D3
63
D4
64
D5
66
D6
67
D7
68
DRVT
Y
P
84
IO
L
83
HDSEL
96
ST
EP
87
DI
R
91
DENS
EL
88
W
R
PRT
99
TR
K
0
97
IN
D
E
X
98
DR0
93
DR1
92
MT
R
0
95
MT
R
1
94
DSK
C
HG
/R
G
73
OS
C1
76
OS
C2
/C
L
K
75
WG
A
T
E
86
W
D
ATA
90
RDAT
A
78
FI
L
T
E
R
82
F
G
ND2
5
0
80
F
G
ND5
0
0
79
SE
T
CUR
85
SL
IN
37
IN
IT
36
AFD
35
STB
33
BUSY
32
PO
E
38
PE
30
SL
C
T
29
ERR
28
HSC0
/C
R
B
6
16
HS
C
1
17
GA
ME
18
G N D A
7 7
G N D B
1 0 0
G N D C
6 5
G N D D
5 9
G N D E
2 7
G N D F
8 9
V C C A
8 1
V C C B
7 4
V C C C
4 5
P
D
/CRD1
34
ACK
31
IC
6
M
51
05
SA9
SA8
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0
VC
C
R1
2
4
4.
7
K
SA
[0
..9
]
AEN-
IR
Q
R
2
IR
Q
R
1
IR
Q
P
DRQ2
TC
RXD1
IR
Q
6
IO
W
-
IO
R
-
RESE
T
DACK2
-
HDSEL
STEP-
RPM
/L
C
WR
P
R
T
-
TR
K
0
-
INDEX-
DR0
-
DR1
-
MT
R
0
-
MT
R
1
-
DS
KCHG/
R
G
WG
ATE-
DI
R
C
118
0
.02
2u
C1
1
9
0.
033
u
R
122
68
0
R1
2
3
2.
2K
C1
1
7
1
000
p
R1
2
1
2
20K
X1
24
M
H
z
WD
AT
A
-
RDAT
A
-
R
105
6.
4
9
K
R
111
1M
SL
INS-
IN
IT
S-
AFD
S
-
T
X
D1
/CRB7
-
CT
S1
-
DSR1
-
DT
R1
-/
CR
B
3
-
RT
S1
-/
CRB4
-
RI
1
-
DC
D1
-
RXD2
T
X
D2
/CRB0
-
CT
S2
-
DSR2
-
DT
R2
-/
CR
B
2
-
RT
S2
-/
CRB1
-
RI
2
-
DC
D2
-
DP[
0
..
7
]
DP7
DP6
DP5
DP4
DP3
DP2
DP1
DP0
R1
0
9
10K
1
HC
S
0
-/
CR
B
6
-
HC
S
1
-
SL
C
T
S
PE
S
B
U
SYS
A
C
KS-
E
RRS-
STBS-
VC
C
J9
3X
1
C1
1
0
15
p
C1
1
1
15p
1
VC
C
J1
8
3X
1
2
3
2
3
VC
C
R1
3
7
10
K
R
138
10K
8
7
6
5
4
3
2
1
A
B
C
D
1
2
3
4
5
6
7
8
D
C
B
A
– 11 –
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