Sharp ER-A880 (serv.man3) Service Manual ▷ View online
2. PIN ASSIGNMENT
Fig. 6 M5105 Pinout Diagram
Table 2 lists the functions of all M5105 pins. A low represents a logic
0 (0 V nominal) and a high represents a logic 1 (+2.4 V nominal).
0 (0 V nominal) and a high represents a logic 1 (+2.4 V nominal).
50
R11
49
R12
48
CTS2
47
DCD2
46
DSR2
45
VDDC
44
DTR2/CRB2
43
RTS2/CRB1
42
SIN2
41
SOUT2/BOUT2/CRB0
40
IRQ3
39
IRQ7
38
POE
37
SLIN
36
INIT
35
AFD
34
VD DD
33
STB
32
BUSY
31
ACK
8
0
F
G
ND2
5
0
7
9
F
G
ND5
0
0
7
8
RD
AT
A
77
VSSA
76
O
S
C
1
75
O
S
C
2
/C
L
K
7
4
V
DDB
7
3
DS
ACH
G
/R
G
72
IR
Q
6
71
T
C
70
D
A
K
69
D
R
Q
68
D
7
67
D
6
66
D
5
65
VSSC
64
D
4
63
62
61
60
59
58
57
56
55
54
53
52
51
C
T
S
1
DC
D1
S
O
UT
1
/BOUT
1
/CRB7
SI
N
1
RT
S
1
/CRB
4
DT
R1
/CRB
3
DS
R1
D3
D2
D1
D0
VSSD
IR
Q
4
1
MR
2
A9
3
A8
4
A7
5
A6
6
A5
7
A4
8
A3
9
A2
10
A1
11
A0
12
AE
N
13
IO
L
14
WR
15
RD
16
HCS0
/CRB
6
17
HCS1
/GW
R/
C
R
PE
18
G
P
E
N
/G
R
D
/X
TSE
L
19
PD
7
20
PD
6
21
PD
5
22
PD
4
23
PD
3
24
PD
2
25
PD
1
26
PD
0
27
V
SSE
28
ER
R
29
SL
C
T
30
PE
81
VDDA
82
FILTER
83
PUMP/PREN
84
DRVTYP
85
SETCUR
86
WGATE
87
STEP
88
RPM/LC
89
VSSF
90
WDA TA
91
DIR
92
DR1
93
DR0
94
MTR1
95
MTR0
96
HDSEL
97
TRK0
98
INDEX
99
WPROT
100
VSSB
M5105
– 4 –
3. PIN DESCRIPTION (M5105)
Pin
Number
Pin Symbol
Pin
Type
Description
11
∼
2
A0
∼
A9
I
I/O Address. Address signals
connected to these inputs
select the active register
during a CPU read or write.
See each individual sections
(UART, parallel port, FDC,
etc.) for details of each
registers.
connected to these inputs
select the active register
during a CPU read or write.
See each individual sections
(UART, parallel port, FDC,
etc.) for details of each
registers.
31
ACK
I
Acknowledge. When set low
by the printer, this input
indicates that the printer has
received data.
by the printer, this input
indicates that the printer has
received data.
12
AEN
I
Address Enable. When high,
this input disables function
selection via A0
this input disables function
selection via A0
∼
A9.
35
AFD
O
Automatic Feed. When low,
this tells the printer to
automatically line feed after
each line printed.
this tells the printer to
automatically line feed after
each line printed.
57, 41
BOUT1,
BOUT2
BOUT2
O
Baud Rate Output. This multi-
function pin gives the
associated serial channel
baudout signal, after data of
10h has been written to the
IIR (interrupt identification
register) and DLAB=1. It also
gives the composite serial
data output signal for the
associated channel after a
reset or after 00h is written to
IIR or DLAB=0.
function pin gives the
associated serial channel
baudout signal, after data of
10h has been written to the
IIR (interrupt identification
register) and DLAB=1. It also
gives the composite serial
data output signal for the
associated channel after a
reset or after 00h is written to
IIR or DLAB=0.
32
BUSY
I
Printer Busy. This input is
set high by the printer when
the printer can not accept
another character.
set high by the printer when
the printer can not accept
another character.
41, 43, 44,
54, 55,
16, 57
54, 55,
16, 57
CRB0
∼
4,
CRB6
∼
7
I/O
Configuration Register Bits.
These dual-function pins act
as inputs during reset (if
CRPE=0) to determine the
state of the configuration
register bits. The bits of the
configuration register is the
complement of these inputs.
A 10K resistor can be used to
pull these pins to the required
signal levels. These pins are
outputs when the chip is not
in reset. These pins have dual
functions, as follows:
SOUT2/CRB0, RTS2/CRB1,
DTR2/CRB2, DTR1/CRB3,
RTS1/CRB4, HCS0/CRB6,
SOUT1/CRB7.
These dual-function pins act
as inputs during reset (if
CRPE=0) to determine the
state of the configuration
register bits. The bits of the
configuration register is the
complement of these inputs.
A 10K resistor can be used to
pull these pins to the required
signal levels. These pins are
outputs when the chip is not
in reset. These pins have dual
functions, as follows:
SOUT2/CRB0, RTS2/CRB1,
DTR2/CRB2, DTR1/CRB3,
RTS1/CRB4, HCS0/CRB6,
SOUT1/CRB7.
Pin
Number
Pin Symbol
Pin
Type
Description
17
CRPE
I/O
Configuration Register
Program Enable. This multi-
function pin selects between
internal or external default
values for the configuration
register and whether the
configuration register can be
initialized through hardware
or software. The chip checks
this pin during reset, at that
time it acts as an input. If it is
low during reset, the
configuration register defaults
to the complement of the
CPB0
Program Enable. This multi-
function pin selects between
internal or external default
values for the configuration
register and whether the
configuration register can be
initialized through hardware
or software. The chip checks
this pin during reset, at that
time it acts as an input. If it is
low during reset, the
configuration register defaults
to the complement of the
CPB0
∼
4, 6, 7 pin states. If it
is high, it defaults to 00h. This
pin must always have a pull
up or pull down resistor (10K)
attached to pull it to the
required signal level. This pin
is driven by the chip when not
in reset. Regardless of the
initial polarity of this pin, the
configuration register can be
programmed whenever
master reset is inactive.
pin must always have a pull
up or pull down resistor (10K)
attached to pull it to the
required signal level. This pin
is driven by the chip when not
in reset. Regardless of the
initial polarity of this pin, the
configuration register can be
programmed whenever
master reset is inactive.
51, 48
CTS1,
CTS2
CTS2
I
Clear to Send. When low,
these inputs indicate that the
modem or data set is ready to
exchange data. CTS is a
modem status input whose
conditions can be tested by
the CPU via reading bit 4
(CTS) of the modem status
register (MSR). Bit 4 is the
complement of CTS. Bit 0
(DCTS) of the MSR shows
whether CTS has changed
state since the previous
reading of the MSR. CTS has
no effect on the transmitter.
Whenever the DCTS bit of the
MSR changes state, an
interrupt is generated if the
modem status interrupts is
enabled.
these inputs indicate that the
modem or data set is ready to
exchange data. CTS is a
modem status input whose
conditions can be tested by
the CPU via reading bit 4
(CTS) of the modem status
register (MSR). Bit 4 is the
complement of CTS. Bit 0
(DCTS) of the MSR shows
whether CTS has changed
state since the previous
reading of the MSR. CTS has
no effect on the transmitter.
Whenever the DCTS bit of the
MSR changes state, an
interrupt is generated if the
modem status interrupts is
enabled.
60
∼
64,
66
∼
68
D0
∼
D7
I/O
Data Bus. This bus contains
eight tri-state input/output
lines. The bus provides
bidirectional communications
between the M5105 chip and
the CPU. Data, control words,
and status information are
transferred via the data bus.
eight tri-state input/output
lines. The bus provides
bidirectional communications
between the M5105 chip and
the CPU. Data, control words,
and status information are
transferred via the data bus.
70
DAK
I
DMA Acknowledge. This is
an active low input used to
acknowledge DMA requests
and to enable the RD and WR
inputs. This signal is enabled
when D3 of the drive control
register is set. The SPECIFY
command must be used to
enable the DMA mode.
an active low input used to
acknowledge DMA requests
and to enable the RD and WR
inputs. This signal is enabled
when D3 of the drive control
register is set. The SPECIFY
command must be used to
enable the DMA mode.
– 5 –
Pin
Number
Pin Symbol
Pin
Type
Description
52, 47
DCD1,
DCD2
DCD2
I
Data Carrier Detect. When
low, this input indicates that
the data carrier has been
detected by the modem or
data set. The DCD signal is a
modem status input whose
condition can be tested by the
CPU by reading bit 7 (DCD)
of the MSR. Bit 7 is the
complement of the DCD
signal. Bit 3 (DDCD) of the
MSR indicates whether DCD
has changed state since the
previous reading of the MSR.
Whenever the DCD bit of the
MSR changes state, an
interrupt is generated if the
modem status interrupt is
enabled. DCD has no effect
on the receiver.
low, this input indicates that
the data carrier has been
detected by the modem or
data set. The DCD signal is a
modem status input whose
condition can be tested by the
CPU by reading bit 7 (DCD)
of the MSR. Bit 7 is the
complement of the DCD
signal. Bit 3 (DDCD) of the
MSR indicates whether DCD
has changed state since the
previous reading of the MSR.
Whenever the DCD bit of the
MSR changes state, an
interrupt is generated if the
modem status interrupt is
enabled. DCD has no effect
on the receiver.
91
DIR
O
Direction. This high drive
open drain output determines
the direction of the head
movement (low = step in, high
= step out). When in the write
or read modes, this output is
high.
open drain output determines
the direction of the head
movement (low = step in, high
= step out). When in the write
or read modes, this output is
high.
93, 92
DR0, DR1
O
Drive. These high drive open
drain outputs are drive select
signals for drives 0 and 1.
They are ANDed with the
corresponding motor enable
lines. These pins contain
encoded drive select
information if bit 7 of the
configuration register is set.
drain outputs are drive select
signals for drives 0 and 1.
They are ANDed with the
corresponding motor enable
lines. These pins contain
encoded drive select
information if bit 7 of the
configuration register is set.
69
DRQ
O
DMA Request. This is an
active high output that signals
the DMA controller that a data
transfer is needed. It is
enabled when D3 of the drive
control register is set. The
SPECIFY command must be
used to enable the DMA
mode.
active high output that signals
the DMA controller that a data
transfer is needed. It is
enabled when D3 of the drive
control register is set. The
SPECIFY command must be
used to enable the DMA
mode.
84
DRVTYP
I
Drive Type. This input is
used by the controller to
enable the 300 kb/s mode. It
enables the use of flexible
drives with either dual or
single-speed spindle motors.
This pin is tied low for dual-
speed motors and tied high
for single-speed motors
(standard AT drives). When
this pin is low, and 300 kb/s
data rate is selected in the
data rate register, the PLL
(phase locked loop) actually
uses 250 kb/s. When high
and 300 kb/s is selected, 300
kb/s is used.
used by the controller to
enable the 300 kb/s mode. It
enables the use of flexible
drives with either dual or
single-speed spindle motors.
This pin is tied low for dual-
speed motors and tied high
for single-speed motors
(standard AT drives). When
this pin is low, and 300 kb/s
data rate is selected in the
data rate register, the PLL
(phase locked loop) actually
uses 250 kb/s. When high
and 300 kb/s is selected, 300
kb/s is used.
Pin
Number
Pin Symbol
Pin
Type
Description
73
DSKCHG/RG
I
Disk Change/Read Gate.
This disk interface input
indicates when the disk drive
door has been opened. The
active high state of this input
is read from bit D7 of address
3F7h. When RG bit in the
mode command is set, this
pin functions as a read gate
signal. When low, it forces the
data separator to lock to the
crystal, and when high it locks
to the data for diagnostic
purposes.
This disk interface input
indicates when the disk drive
door has been opened. The
active high state of this input
is read from bit D7 of address
3F7h. When RG bit in the
mode command is set, this
pin functions as a read gate
signal. When low, it forces the
data separator to lock to the
crystal, and when high it locks
to the data for diagnostic
purposes.
53, 46
DSR1,
DSR2
DSR2
I
Data Set Ready. When low,
this input indicates that the
modem or data set is ready to
establish the communications
link with UART. DSR signal is
a modem status input whose
condition can be tested by the
CPU by reading bit 5 (DSR) of
the MSR. Bit 5 is the
complement of DSR. Bit 1
(DDSR) of the MSR shows
whether DSR has changed
state since the previous
reading of the MSR. When
the DSR bit of the MSR
changes its state, and
interrupt is generated if the
MODEM Status Interrupt is
enabled.
this input indicates that the
modem or data set is ready to
establish the communications
link with UART. DSR signal is
a modem status input whose
condition can be tested by the
CPU by reading bit 5 (DSR) of
the MSR. Bit 5 is the
complement of DSR. Bit 1
(DDSR) of the MSR shows
whether DSR has changed
state since the previous
reading of the MSR. When
the DSR bit of the MSR
changes its state, and
interrupt is generated if the
MODEM Status Interrupt is
enabled.
54, 44
DTR1,
DTR2
DTR2
O
Data Terminal Ready. When
low, this output informs the
modem or data set that the
UART is ready to begin a
communications link. DTR
can be set to an active low by
programming bit 0 (DTR) of
the modem control register
(MCR) to a high level. A
master reset operation sets
this signal to its inactive (high)
state. When the XTSEL pin is
high during reset, the loop
mode operation retains this
signal at its inactive state.
When the XTSEL pin is low
during reset, the associated
pin state is controlled by bit 0
of the MCR during loop mode
operation.
low, this output informs the
modem or data set that the
UART is ready to begin a
communications link. DTR
can be set to an active low by
programming bit 0 (DTR) of
the modem control register
(MCR) to a high level. A
master reset operation sets
this signal to its inactive (high)
state. When the XTSEL pin is
high during reset, the loop
mode operation retains this
signal at its inactive state.
When the XTSEL pin is low
during reset, the associated
pin state is controlled by bit 0
of the MCR during loop mode
operation.
28
ERR
I
Error. This input is set low by
the printer when it has
detected an error.
the printer when it has
detected an error.
82
FILTER
I/O
Filter. This pin is the output of
the charge pump and the
input to the VCO. One or
more filters are attached
between this pin and the
FGND250, FGND500, and
VSSA pins.
the charge pump and the
input to the VCO. One or
more filters are attached
between this pin and the
FGND250, FGND500, and
VSSA pins.
– 6 –
Pin
Number
Pin Symbol
Pin
Type
Description
80
FGND250
O
Filter Ground 250 kb/s. This
low impedance open drain
output connects the PLL filter
for 250K (MFM)/125K (FM)
b/s or 300K (MFM)/150K (FM)
b/s to ground.
low impedance open drain
output connects the PLL filter
for 250K (MFM)/125K (FM)
b/s or 300K (MFM)/150K (FM)
b/s to ground.
79
FGND500
O
Filter Ground 500 kb/s. This
low impedance open drain
output connects the PLL filter
for 500K (MFM)/250K (FM)
b/s to ground.
low impedance open drain
output connects the PLL filter
for 500K (MFM)/250K (FM)
b/s to ground.
18
GPEN
O
Game Port Enable. This
multi-function output gives an
active low signal if I/O
address 201h is read or
written to and the XTSEL pin
was high during reset. It can
be used as a decoded chip
select for external logic that
implements the game port
function in an AT system.
multi-function output gives an
active low signal if I/O
address 201h is read or
written to and the XTSEL pin
was high during reset. It can
be used as a decoded chip
select for external logic that
implements the game port
function in an AT system.
18
GRD
O
Game Read. This multi-
function output provides an
active low signal if I/O
address 201h is selected, the
read pin is low, and the
XTSEL pin was low during
reset. It can be used as a
decoded read signal for
external logic that implements
the game port function in an
AT system.
function output provides an
active low signal if I/O
address 201h is selected, the
read pin is low, and the
XTSEL pin was low during
reset. It can be used as a
decoded read signal for
external logic that implements
the game port function in an
AT system.
17
GWR
O
Game Write. This multi-
function output provides an
active low signal if I/O
address 201h is selected, the
write pin is low, and the
XTSEL pin was low during
reset. It can be used as a
decoded write signal for
external logic that implements
the game port function in an
AT system.
function output provides an
active low signal if I/O
address 201h is selected, the
write pin is low, and the
XTSEL pin was low during
reset. It can be used as a
decoded write signal for
external logic that implements
the game port function in an
AT system.
96
HDSEL
O
Head Select. This high drive
open drain output determines
which disk drive head is
active. Low = Head 1, high
(open) = Head 0.
open drain output determines
which disk drive head is
active. Low = Head 1, high
(open) = Head 0.
16, 17
HSC0,
HSC1
HSC1
O
Hard Disk Chip Select.
These dual and multi-function
outputs provide a fixed disk
enable signal when the
addresses (Table 1) are
present on A0
These dual and multi-function
outputs provide a fixed disk
enable signal when the
addresses (Table 1) are
present on A0
∼
A9 during a
read or write access. Using
minimal hardware, these
signals control and interface
between the CPU and a fixed-
disk drive that has a
controller. HSC0 is always
used for this function after
reset, if XTSEL was high
during reset.
minimal hardware, these
signals control and interface
between the CPU and a fixed-
disk drive that has a
controller. HSC0 is always
used for this function after
reset, if XTSEL was high
during reset.
98
INDEX
I
Index. This pin signals the
beginning of a track.
beginning of a track.
Pin
Number
Pin Symbol
Pin
Type
Description
36
INIT
O
Initialize. This active low
output initializes the printer.
output initializes the printer.
13
IOL
I
I/O Address Low. This input
pin should be driven low by
external decode logic when
all I/O address bits 10
pin should be driven low by
external decode logic when
all I/O address bits 10
∼
15
are low. This signal is gated
inside the M5105 to ensure
that the I/O bus is fully
decoded.
inside the M5105 to ensure
that the I/O bus is fully
decoded.
40, 58
IRQ3, IRQ4
O
Interrupt Requests 3 and 4.
These outputs indicate serial
port interrupts. The
appropriate interrupt goes
high whenever it is enabled
via the interrupt enable
register (IER) and any of the
following serial interrupt
conditions are active: receiver
error flag set, receiver data
available, transmitter holding
register empty, and modem
status set. The interrupt is
reset low upon the
appropriate interrupt service,
disabling through IER or
master reset. IRQ4/IRQ3
present the interrupt signal if
the serial channel is
designated COM1/COM2,
respectively. Both IRQ3 and
IRQ4 can be disabled by
resetting OUT 2 low.
These outputs indicate serial
port interrupts. The
appropriate interrupt goes
high whenever it is enabled
via the interrupt enable
register (IER) and any of the
following serial interrupt
conditions are active: receiver
error flag set, receiver data
available, transmitter holding
register empty, and modem
status set. The interrupt is
reset low upon the
appropriate interrupt service,
disabling through IER or
master reset. IRQ4/IRQ3
present the interrupt signal if
the serial channel is
designated COM1/COM2,
respectively. Both IRQ3 and
IRQ4 can be disabled by
resetting OUT 2 low.
72
IRQ6
O
Interrupt Request 6. This
signals that a flexible-disk
controller operation requires
the attention of the
microprocessor. The action
required depends on the
current function of the
controller. This signal is
enabled when D3 of the drive
control register is set.
signals that a flexible-disk
controller operation requires
the attention of the
microprocessor. The action
required depends on the
current function of the
controller. This signal is
enabled when D3 of the drive
control register is set.
39
IRQ7
O
Interrupt Request 7. This
output indicates parallel port
interrupts. When enabled
(control register bit 4 = 1), the
appropriate interrupt signal
follows the ACK signal input.
output indicates parallel port
interrupts. When enabled
(control register bit 4 = 1), the
appropriate interrupt signal
follows the ACK signal input.
– 7 –
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