Sharp ER-A570 (serv.man7) Service Manual ▷ View online
CHAPTER 3. SRV. RESET AND
MASTER RESET
MASTER RESET
1. SRV. reset (Program Loop Reset)
Used to return the machine back to its operational state after a lock-
up has occurred.
up has occurred.
Procedure
•
Method 1
1) Turn off the AC switch.
2) Set the mode switch to (SRV
′
) position.
3) Turn on the AC switch.
4) Turn to (SRV) position from (SRV
′
) position.
•
Method 2
1) Set the mode switch to PGM2 position.
2) Turn off the AC switch.
3) While holding down JOURNAL FEED key and RECEIPT FEED
key, Turn on the AC switch.
Note: When disassembling and reassembling always power up us-
ing method 1 only. Method 2 will not reset the CKDC4.
Note: SRV programming job#926-B must be set to "4" to allow PGM
program loop reset.
2. Master reset (All memory clear)
There are two possible methods to perform a master reset.
•
MRS-1
Used to clear all memory contents and return machine back to its
initial settings. return keyboard back to default. for default keyboard
layout.
initial settings. return keyboard back to default. for default keyboard
layout.
Procedure
1) Turn off the AC switch.
2) Set the MODE switch to the (SRV
′
) position.
3) Turn on the AC switch.
4) While holding down JOURNAL FEED key, turn to (SRV) position
from (SRV
′
) position.
•
MRS-2
Used to clear all memory and keyboard contents.
This reset returns all programming back to defaults. The keyboard
must be entered by hand.
This reset is used if an application needs different keyboard layout
other than that supplied by a normal MRS-1.
Used to clear all memory and keyboard contents.
This reset returns all programming back to defaults. The keyboard
must be entered by hand.
This reset is used if an application needs different keyboard layout
other than that supplied by a normal MRS-1.
Procedure
1) Turn off the AC switch.
2) Set the MODE switch to the (SRV
′
) position.
3) Turn on the AC switch.
4) While holding down JOURNAL FEED key and RECEIPT FEED
key, turn to (SRV) position from (SRV
′
) position.
5) Key position assignment:
∗
After the execution of MRS-2, only the RECEIPT FEED and
JOURNAL FEED keys can remain effective on key assignment.
Any key can be assigned on any key position on the main key-
board.
JOURNAL FEED keys can remain effective on key assignment.
Any key can be assigned on any key position on the main key-
board.
[key setup procedure]
NOTES:
∗
1: When the 0 key is pressed, the key of the key number on display
is disabled.
∗
2: Push the key on the position to be assigned. With this, the key of
the key number on display is assigned to that key position.
∗
3: When relocating the keyboard, the PGM 1/2 use standard key
layout.
Key number
Key name
Key number
Key name
1
Numeric key "0"
10
Numeric key "9"
2
Numeric key "1"
11
Numeric key "00"
3
Numeric key "2"
12
Numeric key "000"
4
Numeric key "3"
13
Decimal point key
5
Numeric key "4"
14
CL key
6
Numeric key "5"
15
⊗
key
7
Numeric key "6"
16
ST key
8
Numeric key "7"
17
TL key
9
Numeric key "8"
MRS-2
executed
executed
Key position set
Free key
Disable
Free key setup
complete.
complete.
*2
*1
0
0
8
CHAPTER 4. HARD WARE DESCRIPTION
1. Hard ware block diagram
Fig. 1-1
CPU
GATE ARRAY
MPCA5
TTL SIO
DRAWER
MAX.4
MAX.4
PRINTER M-820
STANDARD
RAM1
128KB
OPTIONAL
RAM2
MAX.128KB
ER-01RA:32KB
ER-02RA:128KB
ER-02RA:128KB
STANDARD
ROM
512KB
OPTIONAL
ROM
256KB
ER-A57R1
SWITCH
KEY BOARD
SRN
I/F
1 ports
RS232
I/F
2 ports
ER-A5RS
ER-A6IN
OPT CN
A,B
A,B
CKDC4
SLIP
PRINTER
M-240
SLIP
PRINTER
I/F
ER-31SP
ER-01MB
ER-02RA
ER-02RA
ER-02MB
1 LINE
7DIG 7SEG
7DIG 7SEG
1 LINE
16DIG DOT
16DIG DOT
CUSTOMER DISPLAY
OPERATER DISPLAY
RAM
BOARD
1MB
RAM
BOARD
128KB~
512KB
by 128KB
9
2. Description of main LSI’s
2-1. CPU (HD6415108FX)
1) Pin configuration
HD6415108FX pin configuration
Fig. 2-1
RES
NMI
VSS
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
VSS
A0
A1
A2
A3
A4
A5
A6
A7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
STBY
MD
2
MD
1
MD
0
VC
C
RF
S
H
LWR
HWR
RD
AS
E
VSS
XTAL
EXTAL
VSS
TXD
2
RX
D2
TXD
1
RX
D1
SC
K2
IR
Q
2
IR
Q
1
IR
Q
0
VC
C
AVC
C
P7
3
AN
3
11
2
11
1
11
0
10
9
10
8
10
7
10
6
10
5
10
4
10
3
10
2
10
1
10
0
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
TMCI
P42
P43
FTI1
P45
FTI2
P47
VSS
P50/FTCA1
P51
P52
P53
P54
FMRS
P56
P57/STOP
P60/ER
P61/DR
P62/CS
P63/CD
P64/RR
P65/RS
P66
P67
VSS
AVSS
AN0
AN1
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
78
80
81
82
83
84
A8
A9
A1
0
A1
1
A1
2
A1
3
A1
4
A1
5
VSS
A1
6
A1
7
A1
8
A1
9
A2
0
A2
1
A2
2
A2
3
VSS
WA
IT
BAC
K
BR
EQ
P3
3
P3
4
P3
5
P3
6
P3
7
VC
C
P4
0
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
X
10
2) Block diagram
Fig. 2-2
P47
FTI2
P45
FTI1
P43
P42
P41/TMCI
P40
P37
P36
P35
P34
P33
BREQ
BACK
WAIT
P27/A23
P26/A22
P25/A21
P24/A20
P23/A19
P22/A18
P21/A17
P20/A16
A15
A14
A13
A14
A13
A12
A11
A10
A11
A10
A9
A8
A7
A6
A5
A8
A7
A6
A5
A4
A3
A3
A2
A1
A0
A0
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AVCC
AVSS
MD2
MD1
MD0
RES
STBY
NMI
AS
RD
HWR
LWR
RFSH
EXTAL
XTAL
E
D7
D6
D5
D4
D3
D2
D1
D0
D1
5
D1
4
D1
3
D1
2
D1
1
D1
0
D9
D8
STO
P
/P
5
7
P5
6
FM
R
S
P5
4
P5
3
P5
2
P5
1
P5
0
P6
7
P6
6
RS
/P
6
5
RR/
P
6
4
CD/
P
6
3
CS
/P
6
2
DR/
P
6
1
ER
/P6
0
P7
3
AN
2
AN
1
AN
0
TXD
2
RX
D
2
TXD
1
RX
D
1
SC
K2
IRQ
2
IRQ
1
IRQ
0
H8/500 CPU
DTC
Serial
communication
interface x 2ch
communication
interface x 2ch
8bit timer
16bit free running
timer x 2ch
timer x 2ch
Refresh controller
Wait state
controller
controller
A/D convertor
Interruption controller
Clock
oscillator
oscillator
Watch
dog timer
dog timer
Data bus
Port 1
D
a
ta bu
s (L
ow
er)
D
a
ta bu
s (U
pp
er)
A
d
dr
es
s
bus
Po
rt
2
Po
rt
3
Po
rt
4
Port 5
Port 6
Port 7
Port 8
A
ddr
es
s
bus
X
11
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