Sharp ER-A570 (serv.man7) Service Manual ▷ View online
3) Pin description
Pin
No.
Signal
name
In/
Out
Function
1
RF
Out
Receipt side paper feed solenoid
2
JF
Out
Journal side paper feed solenoid
3
PCUT
Out
Printer (M-820) partial cut signal = Not
used
used
4
FCUT
Out
Printer (M-820) auto cut signal = Not used
5
VF
Out
Multi line validation paper feed = Not
used
used
6
STAMP
Out
Printer (M-820) stamp signal
7
SLFS
Out
Slip printer (M-240) paper feed singnal
8
SLRS
Out
Slip printer (M-240) release signal
9
SLMTD
Out
Slip printer (M-240) motor drive signal
10
RES
Out
Peripheral output reset
11
TRG
Out
Dot head trigger signal (M-240)
12
TRG
Out
Dot head trigger signal (M-820)
13
POFF
In
Interrupt input
14
INT1
In
Interrupt signal (Key interrupt request)
15
HTS1
Out
8 bit serial port output
16
SCK1
Out
Serial port shift clock output
17
STH1
In
8 bit serial port input
18
—
—
Nu
19
—
—
Nu
20
VCC
—
+5V
21
GND
—
GND
22
—
—
Nu
23
VRESC
Out
Turns active when reset and power down
is met
is met
24
SLTMG
In
Slip printer timing signal
25
SLRST
In
Slip printer reset signal
26
AS
In
Address strobe
27
RD
In
Read strobe
28
WR
In
Write strobe
29
φ
In
(
φ
) System clock
30
SDT7
Out
Printhead drive signal (dot7)
31
SDT6
Out
Printhead drive signal (dot6)
32
SDT5
Out
Printhead drive signal (dot5)
33
GND
—
GND
34
SDT4
Out
Printhead drive signal (dot4)
35
SDT3
Out
Printhead drive signal (dot3)
36
SDT2
Out
Printhead drive signal (dot2)
37
SDT1
Out
Printhead drive signal (dot1)
38
D0
I/O
Data bus
39
D1
I/O
Data bus
40
D2
I/O
Data bus
41
D3
I/O
Data bus
42
GND
—
GND
43
D4
I/0
Data bus
44
D5
I/0
Data bus
45
D6
I/0
Data bus
46
D7
I/0
Data bus
47
SPRQ
Out
SSP interrupt request
48
RESET
In
MPCA5 reset
49
INT2
In
Interrupt signal (Nu)
50
INT3
In
Interrupt signal (Nu)
51
RXDI
Out
8 bit serial port output to CPU
52
TXDI
In
8 bit serial port input from CPU
Pin
No.
Signal
name
In/
Out
Function
53
SCKI
In
Serial port shift clock input from CPU.
54
IRQ0
Out
Interrupt request to CPU
55
A0
In
Address bus
56
A1
In
Address bus
57
A2
In
Address bus
58
A3
In
Address bus
59
A4
In
Address bus
60
A5
In
Address bus
61
GND
—
GND
62
VCC
—
+5V
63
A6
In
Address bus
64
A7
In
Address bus
65
A8
In
Address bus
66
A9
In
Address bus
67
A10
In
Address bus
68
A11
In
Address bus
69
A12
In
Address bus
70
A13
In
Address bus
71
A14
In
Address bus
72
A15
In
Address bus
73
A16
In
Address bus
74
A17
In
Address bus
75
A18
In
Address bus
76
A19
In
Address bus
77
A20
In
Address bus
78
A21
In
Address bus
79
A22
In
Address bus
80
—
—
Nu
81
A23
In
Address bus
82
TRGI
In
Dot pulse control/drive signal
83
PTMG
Out
Printer timing signal
84
PRST
Out
Printer reset signal
85
INT4
In
Interrupt signal
86
IPLON
In
Nu
87
MD1
In
Mode select input
88
MD0
In
Mode select input
89
TEST
In
Nu
90
—
—
Nu
91
—
—
Nu
92
—
—
Nu
93
—
—
Nu
94
—
—
Nu
95
—
—
Nu
96
—
—
Nu
97
—
—
Nu
98
—
—
Nu
99
—
—
Nu
100
VCC
—
+5V
101
GND
—
GND
102
—
—
Nu
103
—
—
Nu
104
—
—
Nu
105
—
—
Nu
106
—
—
Nu
16
Pin
No.
Signal
name
In/
Out
Function
107
—
—
Nu
108
WAIT
Out
Wait request signal
109
EXWAIT
In
External wait control input signal
110
RA18
Out
Nu
111
RA17
Out
Nu
112
GND
—
GND
113
RA16
Out
Nu
114
RA15
Out
Nu
115
RDO
Out
Expansion RD signal
Option
116
WRO
Out
Expansion WR signal
117
EXINT3
In
Expansion interruption signal 3
Option
118
EXINT2
In
Expansion interruption signal 2
119
EXINT1
In
Expansion interruption signal 1
120
EXINT0
In
Expansion interruption signal 0
121
OPTCS
Out
Chip select base signal for expansion
option
option
122
ROS1
Out
ROM 1 chip select signal
123
ROS2
Out
ROM 2 chip select signal
124
RAS2
Out
RAM 2 chip select signal
125
RAS1
Out
RAM 1 ship select signal
126
RJRST
In
M820 reset signal
127
RJTMG
In
M820 timing signal
128
DT4
Out
M820 dot signal
129
DT3
Out
M820 dot signal
130
DT2
Out
M820 dot signal
131
DT1
Out
M820 dot signal
132
GND
—
GND
133
DT7
Out
M820 dot signal
134
DT6
Out
M820 dot signal
135
DT5
Out
M820 dot signal
136
RJMTS
Out
M820 motor brake signal
137
RJMTD
Out
M820 motor drive signal
138
—
—
Nu
139
—
—
Nu
140
—
—
Nu
141
—
—
Nu
142
VCC
—
+5V
143
GND
—
GND
144
—
—
Nu
145
RAS3
Out
Nu
146
RJMTR
In
M820 motor lock detection signal
147
SLMTD
In
Nu
148
SLMTS
In
Nu
149
SLMTR
In
GND
150
HTS2
Out
Nu
151
SCK2
Out
Nu
152
STH2
In
Nu
153
—
—
Nu
154
—
—
Nu
155
—
—
Nu
156
—
—
Nu
157
—
—
Nu
158
—
—
Nu
159
DOTEN
Out
Dot drive enable signal
160
—
—
Nu
2-3. CKDC4 (HD404728A20FS)
1) General description
The CKDC4 is a 4-bit microcomputer developed for the ER-A670 and
provides functions to control the real-time clock, keys, and displays.
The basic functions of the CKDC4 are shown below.
provides functions to control the real-time clock, keys, and displays.
The basic functions of the CKDC4 are shown below.
Keys:
The CKDC4 is capable of controlling a maximum of 256
momentary keys. (Sharp 2-key rollover control)
Simultaneous scanning of key and switch
(When a key is scanned, the state of a mode and clerk
switch is also buffered. The host can scan the state of
switch together with the key entry data at the same time
the key is scanned.)
momentary keys. (Sharp 2-key rollover control)
Simultaneous scanning of key and switch
(When a key is scanned, the state of a mode and clerk
switch is also buffered. The host can scan the state of
switch together with the key entry data at the same time
the key is scanned.)
Switches:
Mode switch with 14 positions maximum
8-bit clerk (cashier) switch
2-bit feed switch
1-bit receipt on/off switch
1-bit option switch
4-bit general-purpose switch (1-bit is used for keyboard
select)
8-bit clerk (cashier) switch
2-bit feed switch
1-bit receipt on/off switch
1-bit option switch
4-bit general-purpose switch (1-bit is used for keyboard
select)
Displays:
16-column dot display
12-column 7-segment display (column digit selectable)
All column blink controlled for the dot and 7-segment
display decimal point and indicators
Programmable patterns for 7-segment display:
Four patterns
Internal driver for 7-segment display
12-column 7-segment display (column digit selectable)
All column blink controlled for the dot and 7-segment
display decimal point and indicators
Programmable patterns for 7-segment display:
Four patterns
Internal driver for 7-segment display
Buzzer:
Single tone control
Clock:
Year, month, day of month, day of week, hour, minute
Alarm:
Hour, minute
Interrupt request (event control):
Detection of key input, switch position change, alarm
issue, and counter overflow
issue, and counter overflow
17
Fig. 2-5
2) Pin assignment
Πιν
Νο.
Πορτ
Ι/Ο ΡΕΣΕΤ
Στατε
Σιγναλ
ναµ ε
Ι/Ο Νοτεσ
ΠΥΛΛ
−
ΥΠ
−∆ΟΩΝ
1
Ρ0
1
Ι/Ο
Η−Ζ
ΣΒ
Ο ∆Β4 : ΣΕΓ−Β
ΠΥΛΛ−∆ΟΩΝ
2
Ρ0
2
Ι/Ο
Η−Ζ
ΣΧ
Ο ∆Β4 : ΣΕΓ−Χ
ΠΥΛΛ−∆ΟΩΝ
3
Ρ0
3
Ι/Ο
Η−Ζ
Σ∆
Ο ∆Β4 : ΣΕΓ−∆
ΠΥΛΛ−∆ΟΩΝ
4
Ρ1
0
Ι/Ο
Η−Ζ
ΣΕ
Ο ∆Β4 : ΣΕΓ−Ε
ΠΥΛΛ−∆ΟΩΝ
5
Ρ1
1
Ι/Ο
Η−Ζ
ΣΦ
Ο ∆Β4 : ΣΕΓ−Φ
ΠΥΛΛ−∆ΟΩΝ
6
Ρ1
2
Ι/Ο
Η−Ζ
ΣΓ
Ο ∆Β4 : ΣΕΓ−Γ
ΠΥΛΛ−∆ΟΩΝ
7
Ρ1
3
Ι/Ο
Η−Ζ
ΑΠ
Ο ∆Β7 : 7ΣΕΓ ΧΟΜ
ΠΥΛΛ−∆ΟΩΝ
8
Ρ2
0
Ι/Ο
Η−Ζ
∆∆Π
Ο ∆Β2 : ∆ΟΤ ∆Π
ΠΥΛΛ−∆ΟΩΝ
9
Ρ2
1
Ι/Ο
Η−Ζ
∆Ι∆
Ο ∆Β3 : ∆ΟΤ ΧΟΜ
ΠΥΛΛ−∆ΟΩΝ
10
Ρ2
2
Ι/Ο
Η−Ζ
∆Π
Ο ∆Β5 : 7ΣΕΓ ∆Π
ΠΥΛΛ−∆ΟΩΝ
11
Ρ2
3
Ι/Ο
Η−Ζ
Ι∆
Ο ∆Β5 : 7ΣΕΓ Ι∆
ΠΥΛΛ−∆ΟΩΝ
12
ΡΑ
0
Ι
Ι
ΜΟ∆Ρ
Ι
ΜΟ∆Ε ΡΕΤΥΡΝ
ΠΥΛΛ−ΥΠ
13
ΡΑ
1
Ι
Ι
ΧΦΣΡ
Ι
ΧΛΕΑΡΚ, ΦΕΕ∆,
ΣΩΙΤΧΗ ΡΕΤΥΡΝ
ΠΥΛΛ−ΥΠ
14
Ρ3
0
Ι/Ο
Η−Ζ
ΚΕΞ0
Ο ΚΕΨ ΕΞΧΗΑΝΓΕ0
15
Ρ3
1
Ι/Ο
Η−Ζ
ΚΕΞ1
Ο ΚΕΨ ΕΞΧΗΑΝΓΕ1
16
Ρ3
2
Ι/Ο
Η−Ζ
ΝΥ
Ο ΓΝ∆
17
Ρ3
3
Ι/Ο
Η−Ζ
ΝΥ
Ο ΓΝ∆
18
Ρ5
0
Ι/Ο
I
ΣΤ0
Ο ΚΕΨ ΣΧΑΝ ΣΤ0
19
Ρ5
1
Ι/Ο
Ι
ΣΤ1
Ο ΚΕΨ ΣΧΑΝ ΣΤ1
20
Ρ5
2
Ι/Ο
Ι
ΣΤ2
Ο ΚΕΨ ΣΧΑΝ ΣΤ2
21
Ρ5
3
Ι/Ο
Ι
ΣΤ3
Ο ΚΕΨ ΣΧΑΝ ΣΤ3
22 Ρ6
0
/ΙΝΤ0 Ι/Ο
Ι
ΠΟΦΦ
Ι
Π−ΟΦΦ
23 Ρ6
1
/ΙΝΤ1 Ι/Ο
Ι
ΣΤΟΠ
Ι
ΣΤΟΠ
ΠΥΛΛ−ΥΠ
24 Ρ6
2
/ΙΝΤ2 Ι/Ο
Ι
∆∆ΙΓ
Ο ∆ΟΤ ∆ΙΣΠΛΑΨ ∆ΙΓΙΤ ΙΝΠΥΤ
25 Ρ6
3
/ΙΝΤ3 Ι/Ο
Ι
∆ΧΣ
Ο ∆ΟΤ ∆ΙΣΠΛΑΨ ΧΟΝΤ./ΧΣ
26
ςχχ
Ποωερ συππλψ
27 Ρ4
0
/ΣΧΚ Ι/Ο
Ι
ΣΧΚ
Ι
ΣΧΚ
28
Ρ4
1
/ΣΙ
Ι/Ο
Ι
ΗΤΣ
Ι
ΗΤΣ
29
Ρ4
2
/Σ0
Ι/Ο
Ι
ΣΤΗ
Ο ΣΤΗ
30 Ρ4
3
/ΠΩΜ Ι/Ο
Ι
Σ∆ΙΣΠ
Ι
∆ΙΣΤ ΣΕΛΕΧΤ
31 Ρ7
0
/ΒΥΖΖ Ι/Ο
Ι
ΒΥΖΖ
Ο ΒΥΖΖΕΡ
32 Ρ7
1/
ΣΧΚ2 Ι/Ο
Ι
∆ΣΧΚ
Ο ∆ΟΤ ∆ΙΣΠ ΧΟΝΤ. ΣΧΚ
33
Ρ7
2
/ΣΙ2 Ι/Ο
Ι
ΣΡΕΣ
Ο ΣΨΣΤΕΜ ΡΕΣΕΤ
ΠΥΛΛ−∆ΟΩΝ
Πιν
Νο.
Πορτ
Ι/Ο ΡΕΣΕΤ
Στατε
Σιγναλ
ναµ ε
Ι/Ο Νοτεσ
ΠΥΛΛ
−
ΥΠ
−∆ΟΩΝ
34 Ρ7
3
/Σ02 Ι/Ο
Ο
∆Σ0
Ο ∆ΟΤ ∆ΙΣΠ ΧΟΝΤ. ΣΟ
35
Ρ8
0
Ι/Ο
Ο
ΣΗΕΝ
Ο ΣΗΕΝ
36
Ρ8
1
Ι/Ο
Ο
ΚΡΘ
Ο ΚΕΨ ΡΕΘΥΕΣΤ
37
Ρ9
0
Ι
Ι
ΚΡ0
Ι
ΚΕΨ ΡΕΤΥΡΝ 0
38
Ρ9
1
Ι
Ι
ΚΡ1
Ι
ΚΕΨ ΡΕΤΥΡΝ 1
39
Ρ9
2
Ι
Ι
ΚΡ2
Ι
ΚΕΨ ΡΕΤΥΡΝ 2
40
Ρ9
3
Ι
Ι
ΚΡ3
Ι
ΚΕΨ ΡΕΤΥΡΝ 3
41
ΡΕΣΕΤ
Ι
Ι
ΧΚ∆ΧΡ
Ι
ΧΚ∆Χ Ις ΡΕΣΕΤ
42
ΟΣΧ2
4.19 ΜΗζ Ξ∋ταλ
43
ΟΣΧ1
44
ΓΝ∆
ΓΝ∆
45
ΧΛ1
32.768 ΚΗζ ΟΣΧ
46
ΧΛ2
47
ΤΕΣΤ
Ι
Ι
ςΧΚ∆Χ
5ς
48
∆0
Ι/Ο
Η−Ζ
Γ1
Ο 7 ΣΕΓ ∆ΙΓ 1
ΠΥΛΛ−∆ΟΩΝ
49
∆1
Ι/Ο
Η−Ζ
Γ2
Ο 7 ΣΕΓ ∆ΙΓ 2
ΠΥΛΛ−∆ΟΩΝ
50
∆2
Ι/Ο
Η−Ζ
Γ3
Ο 7 ΣΕΓ ∆ΙΓ 3
ΠΥΛΛ−∆ΟΩΝ
51
∆3
Ι/Ο
Η−Ζ
Γ4
Ι
7 ΣΕΓ ∆ΙΓ 4
ΠΥΛΛ−∆ΟΩΝ
52
∆4
Ι/Ο
Η−Ζ
Γ5
Ο 7 ΣΕΓ ∆ΙΓ 5
ΠΥΛΛ−∆ΟΩΝ
53
∆5
Ι/Ο
Η−Ζ
Γ6
Ο 7 ΣΕΓ ∆ΙΓ 6
ΠΥΛΛ−∆ΟΩΝ
54
∆6
Ι/Ο
Η−Ζ
Γ7
Ο 7 ΣΕΓ ∆ΙΓ 7
ΠΥΛΛ−∆ΟΩΝ
55
∆7
Ι/Ο
Η−Ζ
ΝΥ
Ο
ΠΥΛΛ−∆ΟΩΝ
56
∆8
Ι/Ο
Η−Ζ
ΝΥ
Ο
ΠΥΛΛ−∆ΟΩΝ
57
∆9
Ι/Ο
Η−Ζ
ΝΥ
Ο
ΠΥΛΛ−∆ΟΩΝ
58
∆10
Ι/Ο
Η−Ζ
ΝΥ
Ο
ΠΥΛΛ−∆ΟΩΝ
59
∆11
Ι/Ο
Η−Ζ
ΝΥ
Ο
60
∆12
Ι/Ο
Η−Ζ
ΝΥ
Ο
61
∆13
Ι/Ο
Η−Ζ
ΝΥ
Ο
62
∆14
Ι/Ο
Η−Ζ
ΝΥ
Ο
63
∆15
Ι/Ο
Η−Ζ
ΝΥ
Ο
64
Ρ0
0
Ι/Ο
Η−Ζ
ΣΑ
Ο ∆Β4 : ΣΕΓ−Α
ΠΥΛΛ−∆ΟΩΝ
NOTE 3: Pull-up/down in the table indicates that the lines concerned
require external pull-up/down resistance.
IRQ
SHEN
STH
HTS
SCK
POFF
STOP
SRES
SHEN
STH
HTS
SCK
POFF
STOP
SRES
CKDCR
HOST
SYSTEM
SYSTEM
7SEG-DISPLAY 7DIG
DOT-DISPLAY 16DIG
G1
~
G
7
SA~
SG
P
0
,1
,4
CKDC 4
P2,3
DI
G
0
0
DI
G
1
5
SEG
0
0
SEG
1
5
DOT DISP CONT.
M66004FP
M66004FP
SRES,DCS,DSCK,DSO
ST0~3
KEX0,1
DECODER
LS138
LS138
DECODER
LS138
LS138
KEY BOARD
MAX. 244key
MAX. 244key
DECODER
LS153
LS153
DECODER
LS153
LS153
D
ISP
SL
SK
R
O
Q
BUZZ
BUZZER
CSFR
MOD R
MOD R
KR
0
~
3
18
3. Clock generator
1) CPU (HD6415108FX)
Fig. 3-1
Basic clock is supplied from a 9.83MHz ceramic oscillator.
The CPU contains an oscillation circuit from which the basic clock is
internally driven. If the CPU was not operating properly, the signal
does not appear on this line in most cases.
The CPU contains an oscillation circuit from which the basic clock is
internally driven. If the CPU was not operating properly, the signal
does not appear on this line in most cases.
2) HD404728A20FS CKDC-III oscillation circuit
(Display-PWB)
Fig. 3-2
Two oscillators are connected to the CKDC4.
The main clock X2 generates 4.19MHz which is used during power
on.
When power is turned off, the CKDC4 goes into the standby mode
and the main clock stops.
The sub-clock X1 generates 32.768KHz which is primarily used to
update the internal RTC (real time clock). During the standby mode, it
keeps oscillating to update the clock and monitoring the power recov-
ery.
The main clock X2 generates 4.19MHz which is used during power
on.
When power is turned off, the CKDC4 goes into the standby mode
and the main clock stops.
The sub-clock X1 generates 32.768KHz which is primarily used to
update the internal RTC (real time clock). During the standby mode, it
keeps oscillating to update the clock and monitoring the power recov-
ery.
4. Reset (POFF) circuit
Fig. 4-1
In order to prevent memory loss at a time of power off and power
supply failure of the ECR, the power supply condition is monitored at
all times. When a power failure is met, the CPU suspends the execu-
tion of the current program and immediately executes the power-off
program to save the data in the CPU registers in the external S-RAM
with the signal STOP forced low to prepare for the power-off situation.
The signal STOP is supplied to the CKDC4 as signal RESET to reset
the devices.
This circuit monitors +24V supply voltage.
The voltage at the (–) pin of the comparator GL393 is always main-
tained to 4.3V by means of the zener diode ZD1, while +24V supply
voltage is divided through the resistors R70, R69, and R68, and is
applied to the (+) pin. When normal +24V is in supply, 5.1V is sup-
plied to the (+) pin, therefore, signal POFF is at a high level. When
+24V supply voltage decreases due to a power off or any other
reason, the voltage at the (+) pin also decreases. When +24V supply
voltage drops, the voltage at the (+) pin drops below +4.3V, which
causes POFF to go low, thus predicting the power-off situation.
supply failure of the ECR, the power supply condition is monitored at
all times. When a power failure is met, the CPU suspends the execu-
tion of the current program and immediately executes the power-off
program to save the data in the CPU registers in the external S-RAM
with the signal STOP forced low to prepare for the power-off situation.
The signal STOP is supplied to the CKDC4 as signal RESET to reset
the devices.
This circuit monitors +24V supply voltage.
The voltage at the (–) pin of the comparator GL393 is always main-
tained to 4.3V by means of the zener diode ZD1, while +24V supply
voltage is divided through the resistors R70, R69, and R68, and is
applied to the (+) pin. When normal +24V is in supply, 5.1V is sup-
plied to the (+) pin, therefore, signal POFF is at a high level. When
+24V supply voltage decreases due to a power off or any other
reason, the voltage at the (+) pin also decreases. When +24V supply
voltage drops, the voltage at the (+) pin drops below +4.3V, which
causes POFF to go low, thus predicting the power-off situation.
5. Memory control
1) Memory map
1
All range memory map
Fig. 5-1
CPU
(HD6415108FX)
99
98
XTAL
EXTAL
9.83MHz
X1
43
46
45
15PCH
15PCH
HD404728A20FS
C3
C 4
CKDC 4
OS1
R2
1M
1M
X2
4.19MHz
4.19MHz
CL2
CL1
X1
32.768KHz
32.768KHz
2
1
3
1
2
3
4
IC1A
4069UBD
4069UBD
+5V
IC16
GL393
GL393
-
+
+
RD4.3
+
POFF
CPU
POFF
72
IRQ0
89
RESET (FROM CKDC 4)
STOP (TO CKDC 4)
EL1
+24V
R74
20KG
20KG
ZD1
R70
9.1KG
9.1KG
D10
DSS133
DSS133
R69
9.1KG
9.1KG
R68
4.7KG
4.7KG
2
3
3
1
R67
56K
R66
2.7K
2.7K
MPCA5
13
48
1
C101
1µ
50V
1µ
50V
C99
1000P
1000P
IR
Q
0
54
IN
T
0
Internal I/O
External I/O
Memory image area
External I/O
Memory image area
(*1)
(*2)
(*3)
(*2)
(*3)
RAM area
(10M byte)
(10M byte)
ROM area
(3M byte)
(3M byte)
Expansion I/O area (1M byte)
000000H
1C0000H
800000H
C00000H
FFFFFFH
19
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