Sharp ER-A570 (serv.man7) Service Manual ▷ View online
7. PRINTER control circuit
1)Block diagram
Fig. 7-1
2) General description of the printer controller
The M820 is used as the R/J printer of the body and the M240 is
used as the slip printer. The printer mechanical timing control is made
by the CPU through MPCA5.
used as the slip printer. The printer mechanical timing control is made
by the CPU through MPCA5.
3) Motor drive circuit
Fig. 7-2
Fig. 7-3
The printer motor ON/OFF control is performed with RJMTD as the
drive signal and RJMTS as the brake signal. Motor lock detection is
performed as follows:
Check by the hardware: The motor drive current flowing from the
MTD transistor is checked across R126. When an overcurrent is de-
tected, the MTR signal becomes HIGH to drive the MTS and MTD
signals in the MPCA5 to HIGH impedance to stop conduction of the
motor.
When the motor is stopped, the CPU timing pulse width is extended
and the CPU judges it as motor lock.
CPU motor lock detection can be read out as internal register MTLK.
Lock can be released by writing dummy data into MTLK as well as by
conventional hardware reset.
drive signal and RJMTS as the brake signal. Motor lock detection is
performed as follows:
Check by the hardware: The motor drive current flowing from the
MTD transistor is checked across R126. When an overcurrent is de-
tected, the MTR signal becomes HIGH to drive the MTS and MTD
signals in the MPCA5 to HIGH impedance to stop conduction of the
motor.
When the motor is stopped, the CPU timing pulse width is extended
and the CPU judges it as motor lock.
CPU motor lock detection can be read out as internal register MTLK.
Lock can be released by writing dummy data into MTLK as well as by
conventional hardware reset.
Check by the CPU: When timing pulse from the printer is not gener-
ated for more than the specified time, the CPU
judges it as motor lock, the MTON is reset (To
High) and the motor is stopped.
judges it as motor lock, the MTON is reset (To
High) and the motor is stopped.
4) Printhead mechanism
With the timing plus (TS) from the motor, current is applied to the dot
wire drive coil to print.
wire drive coil to print.
•
Discussion is given here to explain how a single dot wire is driven.
1
When current is applied to a coil, the actuator moves towards
the arrowhead (a) as the steel core is magnetized. The actua-
tor makes connection with the wire, and the wire pushed out
towards the platen.
the arrowhead (a) as the steel core is magnetized. The actua-
tor makes connection with the wire, and the wire pushed out
towards the platen.
2
As the wire hits the platen with the ink ribbon and paper in-be-
tween, a dot is then printed.
tween, a dot is then printed.
3
When current is removed from the coil, the actuator and the
wire return to their home positions by means of the actuator
spring and wire return spring.
wire return to their home positions by means of the actuator
spring and wire return spring.
Fig. 7-4
5) Dot wire drive control circuit
Fig. 7-5
When writing is made into address 00FF91H by the dot register inj
MPCA5, dot wire drive signals DT1~DT7 are formed.
When PMD1 is low, the R/J printer is selected.
MPCA5, dot wire drive signals DT1~DT7 are formed.
When PMD1 is low, the R/J printer is selected.
CPU
Data
bus
bus
MPCA5
DRIVER
PRINTER
(M-820)
(M-820)
RECEIVER
Address bus
SLIP PRINTER
I/F PWB
(OPTION)
MPCA5
M
136 RJMTS
MTR
+5V
R97
+24V
137 RJMTD
RJMTR
(SLMTR)
SLMTD
RJMTD
RJMTS
(SLMTD)
(SLMTS)
MTD
MTS
MTON
MTLK
SMTLK
PMD1
S92
WE
WE
D7I
D1I
D0I
D0I
PMD1 = "1": Slip printer
PMD1 = "0": R/J printer
PMD0 = "0": R/J printer
PMD0 = "1": Validation printer
PMD1 = "0": R/J printer
PMD0 = "0": R/J printer
PMD0 = "1": Validation printer
MPCA5 internal circuit
MTON=1: ON
Motor
ON
MTON
ON
MTON
register
Timing
circuit
circuit
Select *
Print
mode
mode
PMD1~
PMD0
PMD0
Motor lock flag
MTLK, SMTLK
MTLK, SMTLK
Wire resetting spring
Nose print head
Dot wire
Intermediate
guides
guides
Ink
ribbon
ribbon
Paper
Platen
Fulcrum
Drive coll
Actuator plate
Wire tip guide
(or a hard stone)
(or a hard stone)
S91
WE
PMD1
R/J DT1~7
SLIP SDT1~7
Dot output
port
DT7~DT1
00FF91H
port
DT7~DT1
00FF91H
MPCA5 internal circuit
24
6) Print trigger generating circuit
MPCA5 internal circuit
Fig. 7-6
•
Automatic trigger mode selection register (TRGE)
TRGE = 1:
Automatic trigger generation
TRGE = 0:
Trigger is generated at change edge of OCRA
matchoutput.
(Reset initial value = 0)
matchoutput.
(Reset initial value = 0)
•
Timing pulse active edge select register (EDGE)
EDGE = 0:
Falling edge
EDGE = 1:
Rising edge
(Reset initial value = 0)
(Reset initial value = 0)
7) Dot solenoid drivers (solenoid 1 - 7)
Fig. 7-7
Current to the dot solenoid is controlled in the following manner:
•
VRES must be at a high level.
•
At the same time DTS1 is set low, TRG must be set low.
•
PRTE is now set low. (MPCA5)
•
PE must be set high level.
•
The signal is turned high at point @, the magnet driver output is
set low, and then VH flows through the magnet driver.
set low, and then VH flows through the magnet driver.
•
The dot wire now protrudes to hit and print.
8) Sensor signal receive circuit
Fig. 7-8
MPCA5 internal circuit
Fig. 7-9
The signal from the photocoupler within the printer is converted into
TTL level and conveyed to the MPCA5.
TTL level and conveyed to the MPCA5.
9) Paper feed, stamp and cutter circuit
Fig. 7-10
The paper feed/stamp related signals issued from MPCA5 and pulled
up by the VRES signal to prevent action when the power supply is not
steady.
up by the VRES signal to prevent action when the power supply is not
steady.
Fig. 7-11
CK
D
Q
Q
R
CK
D
R
Q
CK
D
00FF97H
TRG
TRGE
EDGE
S97
WE
D2I
PTMG
TRGI
Φ
RST
S97
WE
D1I
RST
PMD1
TRG
Edge
select
select
Edge
detection
S91
write
Dot register write detection
90us delay
timer
4µ±1
timer
timer
S97 write
PRTE
D T1
DT7
MPCA5
@
VRES
STA401A
D OT1
DOT7
VH (+24V)
1
10
R78
R81
C104
RJTS
RJT 127
RJR 126
R79
R80
RJRSTS
RJTMG
MPCA5
RJRST
C105
PTMG
S97
WE
D0I
RST
PMD1
CK
D
Q
R
CAPS
00FF97H
RJTMG
RJRST
(SLTMG)
(SLRST)
00FF97H
* Capture
FIX terminal
FIX terminal
Capture
select
gate
select
gate
Noise
killer
logic
killer
logic
Select
gate
gate
Pulse status
flag
flag
** PRST/PTMG is in the same phase (non-reversion) of RJTMG/RJRST.
CAPS=0: PST
CAPS=1: TMG
CAPS=1: TMG
PTMG
PRST
PFRO
PFR
PFJO
STMPO
MPCA5
VRES
STMP
PFJ
KTD1414
RECEIPT FEED
JOURNAL FEED
STAMP
+24V
TD62308F
(PCUTO)
(FCUTO)
PCUT
FCUT
STA401A
STAMP
FCUT
PCUT
JF
RF
VF
(SLRS)
(SLF)
S93
WE
S94
S95
MTD
MTLK
Control gate
+10ms delay
RJ port *
00FF93H
00FF93H
VAL port *
00FF94H
00FF94H
Slip port *
00FF95H
00FF95H
25
Printer control signals are generated by writing each port address into
the register address in PMCA5.
the register address in PMCA5.
CAUTION
If fuse F2 should be blown, the dot head solenoid may be shorted. Be
sure to check the head impedance and driver breakdown.
sure to check the head impedance and driver breakdown.
When fuse F2 is blown:
1
Remove F2, and perform the service resetting. The set the mode
switch to a position other than SRV and SRV’ and turn off the
power.
switch to a position other than SRV and SRV’ and turn off the
power.
2
Install fuse F2 (1.5A)and turn on the power.
If the fuse blows with the above operation, driver STA401A may
be shorted.
If the fuse blows with the above operation, driver STA401A may
be shorted.
3
Turn off the power.
4
Disconnect the printer cable from the printer. Measure impedance
between the printer body connector pin 21 and the following pins:
18, 20, 24, 25, 28, 29, 30
The impedance must be 12.4
between the printer body connector pin 21 and the following pins:
18, 20, 24, 25, 28, 29, 30
The impedance must be 12.4
∼
18
Ω
.
If impedance is outside the above range, the dot solenoid is bad.
Replace the dot head unit.
Replace the dot head unit.
8. Drawer drive circuit
Fig. 8-1
The drawer is directly supported by the CPU. No action starts when
the power supply is not steady as the output stage of the driver is
pulled VP by VRES signal.
Drawer open and close is sensed with the microswitch provided in the
drawer whose signal is level converted with R75 and R77 and directly
read by the CPU.
the power supply is not steady as the output stage of the driver is
pulled VP by VRES signal.
Drawer open and close is sensed with the microswitch provided in the
drawer whose signal is level converted with R75 and R77 and directly
read by the CPU.
9. Key, display, timer, buzzer controls
The keys, switches, displays, timer/calendar, and buzzer are control-
led by the CKDC-4 on the display PWB.
led by the CKDC-4 on the display PWB.
Block diagram
Fig. 9-1
DR0
DRAW0
52
50
DOPS
C103
1000P
R75
1K
1K
TD62308F
R77 4.7K
51
53
54
DR3
DR2
DR1
DRAW1
DRAW2
DRAW3
VRES
CPU
+24V
Drawer
solenoid
solenoid
+24V
R76
47K
47K
IRQ
SHEN
STH
HTS
SCK
POFF
STOP
SRES
SHEN
STH
HTS
SCK
POFF
STOP
SRES
CKDCR
HOST
SYSTEM
SYSTEM
7SEG-DISPLAY 7DIG
DOT-DISPLAY 16DIG
G1~G7
SA
~
S
G
P0
,1
,4
CKDC 4
P2,3
DI
G
0
0
DI
G
1
5
SE
G
0
0
SE
G
1
5
DOT DISP CONT.
M66004EP
M66004EP
SRES,DCS,DSCK,DSO
ST0~3
KEX0,1
DECODER
LS138
LS138
DECODER
LS138
LS138
KEY BOARD
MAX. 244key
MAX. 244key
DECODER
LS153
LS153
DECODER
LS153
LS153
D
ISPS
L
SK
R
O
Q
BUZZ
BUZZER
CSFR
MODR
MODR
KR
0
~
3
26
1) Power on/off sequence
Fig. 9-2
Hatched area indicates logic unstable.
<At power on>
When +24V power rises, the signal POFF is forced high (A), by which
time the +5V supply becomes stable. The CKDC-III monitors the state
of POFF while updating the timer/calendar in the low power standby
mode, and when the high state of POFF is detected, the system reset
signal (RESET) is set high (B), by which time the output lines STOP
and SCK of the CPU and MPCA5 have been initialized to high, re-
spectively (C). Thereafter, the CKDC-III sets SHEN active (low) (D) to
notify the CPU of the command/data communication ready state.
One byte data/command can be transferred with eight SCK pulses
(F). When one byte has been transferred with eight SCK pulses, the
CKDC-III sets SHEN high to initiate internal processing. After comple-
tion of the internal processing, when the next byte transfer becomes
ready, the CKDC-III sets SHEN back to a low state to wait for the next
byte transfer (G).
Thereafter, the SHEN and SCK timing described above is repeated to
carry on the communication.
time the +5V supply becomes stable. The CKDC-III monitors the state
of POFF while updating the timer/calendar in the low power standby
mode, and when the high state of POFF is detected, the system reset
signal (RESET) is set high (B), by which time the output lines STOP
and SCK of the CPU and MPCA5 have been initialized to high, re-
spectively (C). Thereafter, the CKDC-III sets SHEN active (low) (D) to
notify the CPU of the command/data communication ready state.
One byte data/command can be transferred with eight SCK pulses
(F). When one byte has been transferred with eight SCK pulses, the
CKDC-III sets SHEN high to initiate internal processing. After comple-
tion of the internal processing, when the next byte transfer becomes
ready, the CKDC-III sets SHEN back to a low state to wait for the next
byte transfer (G).
Thereafter, the SHEN and SCK timing described above is repeated to
carry on the communication.
<At power off>
When +24V power drops, POFF goes low (H).
A low on the POFF line causes a low level interrupt request which is
sent the IRQ0 pin of the CPU. Within a maximum of 10msec of the
low level IRQ0 input, the CPU performs software processing neces-
sary for power-off, after which the STOP output is set low (I).
When STOP goes low, the CKDC-III sets RESET low to reset the
whole system (J). And, the +5V supply is held at 4.75V or higher
voltage, after which the voltage drops to a level that the logic circuit
does not operate.
A low on the POFF line causes a low level interrupt request which is
sent the IRQ0 pin of the CPU. Within a maximum of 10msec of the
low level IRQ0 input, the CPU performs software processing neces-
sary for power-off, after which the STOP output is set low (I).
When STOP goes low, the CKDC-III sets RESET low to reset the
whole system (J). And, the +5V supply is held at 4.75V or higher
voltage, after which the voltage drops to a level that the logic circuit
does not operate.
2) Key and switch scanning
Strobes ST0 ~ ST3 are decoded on the keyboard by two 74LS138 3-
to-8 decoders to generate 16 strobe signals of S15 ~ S0.
The key matrix consists of 16 strobe lines and 16 returns lines of
KR0A, KR1A, KR2A, KR3A, KR0B, KR1B, KR2B, and KR3B.
To minimize interfacing lines between the CKDCIII and the keyboard
unit, two multiplexers (74HC153) are used to multiplex signals by the
timing controlled with the signals KEX0 and KEX1 which are sent to
the CKDCIII on the return lines of KR0 ~ KR3.
to-8 decoders to generate 16 strobe signals of S15 ~ S0.
The key matrix consists of 16 strobe lines and 16 returns lines of
KR0A, KR1A, KR2A, KR3A, KR0B, KR1B, KR2B, and KR3B.
To minimize interfacing lines between the CKDCIII and the keyboard
unit, two multiplexers (74HC153) are used to multiplex signals by the
timing controlled with the signals KEX0 and KEX1 which are sent to
the CKDCIII on the return lines of KR0 ~ KR3.
Timing ST
Fig. 9-3
The mode switch in provided with a special return line MODR, apart
from the above return lines.
In the same manner, the clerk, paper feed key (J/R), and receipt
on/off switches use CFSR as the return line.
from the above return lines.
In the same manner, the clerk, paper feed key (J/R), and receipt
on/off switches use CFSR as the return line.
3) DISPLAY CONTROL
Fig. 9-4
CKDC4 directly drives the 7-segment display unit and the dot display
is driven via M66004FP.
is driven via M66004FP.
<7-segment display>
Fig. 9-5
A
B
C
D
G
I
J
E
F
H
+5V
POFF
RESET
STOP
SHEN
SCK
+24V
12.45ms
778µ S
10µ S 10µ S 10µ S
KR0A
KR3A
KR0B
KR3B
80µ S
ST3
S15
ST2
ST1
ST0
S14
ST0
KEX0
KEX1
KR0~KR3
S//
RES
DSO
DSCK
DCS
+5V
DG0~
DG15
Display
controller
M66004
EP
DDIG
SO2
SCK2
SDISP
SA~SG
DP,ID
G1~7
7SEG-Display
D0~D34
DOT-Display
16
CKDC 4
976µS
15µS
44.8µS
58µS
Gm
SA,SB,SC,SD
SE,SF,SG
SE,SF,SG
DP,ID
Gm+1
976µS x n
27
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