Sharp ER-A450 (serv.man2) Service Manual ▷ View online
<Motor lock protection>
When an abnormal load is applied to the mechanism, the DP (Dot
Pulse) frequency is checked to prevent against the motor burn-out,
the timing belt shift, and gear damage. If the following condition is
made, the CPU stops the motor rotation.
Pulse) frequency is checked to prevent against the motor burn-out,
the timing belt shift, and gear damage. If the following condition is
made, the CPU stops the motor rotation.
When starting the motor: When the cycle from starting to the
100th pulse of DP is 16ms. (The one pulse cycle of DP is normally
555us.)
100th pulse of DP is 16ms. (The one pulse cycle of DP is normally
555us.)
During constant rotation of the motor: When one pulse of DP is
1100us or more.
1100us or more.
4) Printer sensor circuit
The printer supplies the RP (Reset Pulse) signal, the HP (Home
Position) signal, and the DP (Dot Pulse) signal) to control printing
timing and conduction timing of solenoids. It also supplies the VPJ
signal to detect the presence of validation paper. These sensor are
photo interrupters.
Position) signal, and the DP (Dot Pulse) signal) to control printing
timing and conduction timing of solenoids. It also supplies the VPJ
signal to detect the presence of validation paper. These sensor are
photo interrupters.
RP (RJRST) signal
This signal is outputted once for every reciprocating motion of the
print head. It indicates the reference position of the HP signal.
This signal is outputted once for every reciprocating motion of the
print head. It indicates the reference position of the HP signal.
The rear edge of RP (OFF -- ON) is used as the signal.
HP signal
The pulse signal is outputted from the slit in the disk installed to
the DC motor shaft. It is used as the reference signal for starting
counting of the DP signal. It is generated once for twenty DP
signals. The rear edge of the HP signal (ON -- OFF) immediately
after generation of the RP signal is used as the signal.
The pulse signal is outputted from the slit in the disk installed to
the DC motor shaft. It is used as the reference signal for starting
counting of the DP signal. It is generated once for twenty DP
signals. The rear edge of the HP signal (ON -- OFF) immediately
after generation of the RP signal is used as the signal.
DP (RJTMG) signal
The pulse signal is outputted from the slit in the disk installed to
the DC motor shaft. It is used as the control signal for the print
solenoid and the paper feed solenoid.
The pulse signal is outputted from the slit in the disk installed to
the DC motor shaft. It is used as the control signal for the print
solenoid and the paper feed solenoid.
The front edge of the output signal (ON -- OFF) is used as the
signal.
signal.
VPJS (VPJ) signal
The presence of a validation card is detected by interruption of the
photo interrupter LED light by the validation card.
The presence of a validation card is detected by interruption of the
photo interrupter LED light by the validation card.
5) Dot solenoid drive circuit
The DOT1
∼
DOT7 (the dot solenoid drive signals from the MPCA7)
are pulled up by the VRESE and converted into LOW by the driver IC.
A +24V voltage is applied to the solenoid. This operates the dot wire.
A +24V voltage is applied to the solenoid. This operates the dot wire.
6) Paper feed circuit
The PFJ0 (the journal paper fed signal from the MPCA7) and the
PFR0 (the receipt paper feed signal) are pulled up by the VRESE and
converted into LOW level. A +24V voltage is applied to the solenoid.
This operates the paper feed solenoid.
PFR0 (the receipt paper feed signal) are pulled up by the VRESE and
converted into LOW level. A +24V voltage is applied to the solenoid.
This operates the paper feed solenoid.
R207
Q6
C93
+5V
R206
R126
HP
HP
+5V
R132
Q8
C91
+5V
R131
R130
RJTMG
DP
+5V
C228
+5V
RJRST
RP
+5V
VPS
VPJS(NU)
+5V
R129
R133
MPCA7
CPU
R1134
NOT USED
OFF
ON
555µs(TYP.)(516~590µS)
#1 #2 #3 #4
+5V
GND
+5V
GND
ON
ON
+5V
GND
OFF
OFF
RP
HP
DP
Relation ship among RP/HP/DP
1.5ms or above
The first HP after turning
OFF/ON RP.
OFF/ON RP.
20 cycles of DP (TYP.11.1ms)
50µs above
50µs above
Print area
* The waveforms are those indicated with arrow in Fig.3-3.
VRESC
R146
R145
Q9
R149
DOT1
~DOT4
~DOT4
IC15
DOT1~DOT4
IC16
DOT5~DOT7
DOT5
~DOT7
~DOT7
MPCA7
+5V
+24V
R152
R153
R155
R155
VRESC
R146
R145
Q9
PFJ0
PFJ0
PFR0
MPCA7
+5V
+24V
PFR0
Q11
F2
IC16
IC18
R156
R161
4 – 14
7) Caution
CAUTION
If fuse F2 should be blown, the dot head solenoid may be shorted. Be
sure to check the head impedance and driver breakdown.
sure to check the head impedance and driver breakdown.
When fuse F2 is blown:
Remove F2, and perform the service resetting. The set the mode
switch to a position other than SRV and SRV’ and turn off the
power.
switch to a position other than SRV and SRV’ and turn off the
power.
Install fuse F2 (1A) and turn on the power.
If the fuse blows with the above operation, driver 4AC16 may be
shorted.
If the fuse blows with the above operation, driver 4AC16 may be
shorted.
Turn off the power.
Disconnect the printer cable from the printer. Measure impedance
between the printer body connector pin 5 and the following pins:
1, 3, 9, 11, 13, 21, 25
The impdenace must be 10.5
between the printer body connector pin 5 and the following pins:
1, 3, 9, 11, 13, 21, 25
The impdenace must be 10.5
Ω
±
10%.
If impedance is outside the above range, the dot solenoid is bad.
Replace the dot head unit.
Replace the dot head unit.
8. Drawer drive circuit
Fig. 8-1
The drawer is directly supported by the CPU. No action starts when
the power supply is not steady as the output stage of the driver is
pulled VP by VRESC signal.
the power supply is not steady as the output stage of the driver is
pulled VP by VRESC signal.
Drawer open and close is sensed with the microswitch provided in the
drawer whose signal is level converted with R74 and R73 and directly
read by the CPU.
drawer whose signal is level converted with R74 and R73 and directly
read by the CPU.
9. Key, display, time buzzer controls
Fig. 9-1
1) Power on sequence
During service interruption, the CKDC8 senses POF within 500msec.
When service interruption is cancelled by turning on the power, the
CKDC8 cancels resetting of the CPU in the command mode. After
initializing each port, the CPU reads the start condition (1 byte).
When service interruption is cancelled by turning on the power, the
CKDC8 cancels resetting of the CPU in the command mode. After
initializing each port, the CPU reads the start condition (1 byte).
Fig. 9-2
After sampling POF High, the CKDC5 performs mode scan and key
scan at
scan at
, then cancels resetting of the CPU. After being cancelled,
the CPU initializes each port at
and reads the start condition.
After being cancelled, the CPU reads the start condition without fail to
set the sift mode. If, however, the first starting is made in other than
SRV mode after the CKDC8 resets the CPU without request from the
CPU, the CKDC8 sets the start condition supposing that starting is
made in SRV mode.
set the sift mode. If, however, the first starting is made in other than
SRV mode after the CKDC8 resets the CPU without request from the
CPU, the CKDC8 sets the start condition supposing that starting is
made in SRV mode.
VCOM
5
VCOM
7
VCOM
17
VCOM
23
DOT3
1
3
9
11
13
21
25
DOT7
DOT5
DOT2
DOT1
DOT4
DOT6
DOT1~DOT7
+24V
DR0
DRAW0
52
50
DOSP
C97
1000P
R144
1K
1K
TD62308F
R143 4.7K
51
DR1
DRAW1
VRESC
CPU
+24V
Drawer
solenoid
solenoid
+24V
R42
47K
47K
IC18
KR0~7,KR10,KR11
ST0~ST7
ST0~ST7
G1~G10
T0~T9
RES0
RESET
VDD
RES0
a~g,DP
KR0~KR7
KR10,KR11
a~g,DP
Key board
Display
CKDC 8
VCC
B
BUZZER
2
Driver
Driver
HTS1
SCK1
RESET
INT2
POFF
HTS
SCK
RESET
HTS
SCK
RES1
RES1
CPU
MPCA7
STH1
STH
STH
P11
P12
RES
LDRQ
SHEN
LDRQ
SHEN
P10
ERC
ECR
P-OFF
POFF
POF
RES1
SHEN
LDRQ
1
2
Start condition
Next command
4 – 15
2) Power off sequence
When the CPU senses a service interruption, it performs necessary
procedures for CPU stop. Then the CPU outputs a reset request to
the CKDC5.
procedures for CPU stop. Then the CPU outputs a reset request to
the CKDC5.
Reset request
Fig. 9-3
When the CPU senses a service interruption or an error, it performs
necessary procedure for CPU stop and issues reset request.
necessary procedure for CPU stop and issues reset request.
CPU procedures necessary for reset request
All CPU interrupts are made DI.
SCK is driven to low.
Keep LDRQ at LOW level for 20usec or more and drive it HIGH.
Loop
to
. During looping, access should not be made to
external memory.
It should be within 140usec from rising of one LDRQ to rising of
another.
another.
When, however, the CKDC8 senses a service interruption at POF, it
stops displaying. Service interruption procedure is performed after
receiving reset request from the CPU. If reset request is not sent from
the CPU within 100msec the service interruption procedure is started
after 110
stops displaying. Service interruption procedure is performed after
receiving reset request from the CPU. If reset request is not sent from
the CPU within 100msec the service interruption procedure is started
after 110
±
10msec to go into the stand-by mode.
Fig. 9-4
3) Key and switch scanning
Fig. 9-5
As the strobe signal, 8 bits of ST0 - 8 are used.
KR0 - KR7 are used as the key return signal. KR10 is used as the
return signal of the paper feed key, cashier key and MRS switch.
KR11 is used as the return signal of the mode switch.
return signal of the paper feed key, cashier key and MRS switch.
KR11 is used as the return signal of the mode switch.
4) DISPLAY CONTROL
Fig. 9-6
CKDC8 directly drives the LED display unit.
10. Power supply circuit
Fig. 10-1
+24V:
Printer, solenoid power
+5V:
VCC (Logic power)
VDD:
Battery charge, Battery back-uped power, CKDC-8 and
RAM Back-up power
RAM Back-up power
20µsec or more
SCK
LDRQ
SHEN
DON'T CARE
TH
20µsec or more
TL
TL+TH 140µsec
<
=
RES1
POF
RES1
110±10msec
356.25µsec
38µsec
KR0~KR7
KR10,KR11
ST0
ST9
CKDC5
G1-G10
SA-SG,DP
SA-SG,DP
LED-display
(for custmer)
(for custmer)
LED-display
(for operator)
(for operator)
Driver
Power
trans.
trans.
DC-DC
Converter
circuit
Battery
circuit
circuit
+5V
F1
F2
Switching
regulator
+24V
+
-
~
~
VDD
4 – 16
CHAPTER 5. TEST FUNCTION
1. General
1) This diagnostic program has been developed for diagnosing ma-
chine functions in the field. The program is contained within the
ER-A440.
The diagnostic program is stored in the external ROM which will
be executed by the CPU (H8/510) which requires the following
diagnostic operations:
ER-A440.
The diagnostic program is stored in the external ROM which will
be executed by the CPU (H8/510) which requires the following
diagnostic operations:
a) Proper power supply voltages are mandatory for logic circuits
(+5V, VDD, POFF, +24V).
b) CPU input/output pins, CPU internal logic, CKDC8, MPCA7,
system bus and common ROM/RAM must be working prop-
erly.
erly.
2. Operational procedure
To start the diagnostic program, you must enter the following com-
mand.
3-digit test item number
mand.
3-digit test item number
→
key in the SRV mode.
The key assignment must be properly set and the ROM and RAM
must be operating properly to go into this mode. This is necessary
because the control jumps to the program area in the SRV mode. A
master reset must be performed before operating the ECR for the first
time. After any option is installed, a program reset is required. When
the master reset or program reset is performed, be sure to check the
printout on the journal paper.
must be operating properly to go into this mode. This is necessary
because the control jumps to the program area in the SRV mode. A
master reset must be performed before operating the ECR for the first
time. After any option is installed, a program reset is required. When
the master reset or program reset is performed, be sure to check the
printout on the journal paper.
Master reset:
Turn power on in the SRV’ mode and change it
to the SRV mode with the JF key pressed.
to the SRV mode with the JF key pressed.
Journal print:
MASTER RESET ***
Program reset: Turn power on in the SRV’ mode and change it
to the SRV mode.
Journal print:
PRG. RESET ***
3. Test command list
With the SRV mode and the following test code entry, the test start.
CODE
DESCRIPTION
100
Display & Buzzer test
101
Key code & Cashier key test
102
R/J printer test
104
Keyboard test
105
Mode switch test
106
Printer sensor test
108
Calendar osckllator test
109
SSP test
110
Drawer open sensor test (For standard drawer)
111
Drawer open sensor test (For remote drawer)
120
Standard RAM test
130
Standard ROM test
150
Printer dot pulse width adjustment
200
Option RAM test
500
RS-232 loop back test
4. Test contents
[1] Display & Buzzer test
1) Key operation
2) Functional description
Display the following message on the front and the rear display
boards.
boards.
A decimal point shifts from lower number of digit by one digit (per
200m sec.).
200m sec.).
Next, display the following segments (for approx. 1 sec.).
Repeat the above two kinds of displays.
Sound a buzzer continuously during test.
3) Check items
a) The display must be correctly shown at each position.
b) The luminosity of displays must be uniform and even at each
position.
c) Abnormal buzzer sound is not allowed.
4) Test termination
Press any key. The test terminates with the test and message printed
[2] Key code & Cashier key test
1) Key operation
2) Functional description
Key code, MRS switch state and Cashier code are displayed.
100
TL
1. 2. 3. 4. 5. 6. 7. 8. 9. 0.
8. 8. 8. 8. 8. 8. 8. 8. 8. 8.
1 0 0
101
TL
(Not used)
Key code
(Cashier code)
5 – 1
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