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This circuit monitors +24V supply voltage.

The voltage at the (–) pin of the comparator IC3A is always main-
tained to 5.1V by means of the zener diode ZD2, while +24V supply
voltage is divided through the resistors R12, R13, and R14, and is
applied to the (+) pin. When normal +24V is in supply, 6.8V is sup-
plied to the (+) pin, therefore, signal POFF is at a high level. When
+24V supply voltage decreases due to a power off or any other
reason, the voltage at the (+) pin also decreases. When +24V supply
voltage drops, the voltage at the (+) pin drops below +5.1V, which
causes POFF to go low, thus predicting the power-off situation.

The STOP signal from the CPU is converted into the RESETS signal
by the CKDC6.

The  RESETS signal from the CKDC8 is converted into the RESET
 signal at the gate backed-up by the VRAM power, performing the
system reset.

Fig. 5-1

( 1)  “Internal I/O” means the registers in the H8/510.

( 2)  “External I/O” means the base system I/O area to be ad-

dressed in page 0. 

( 3) "Memory image area" means the lower 32KB of ROM area

which is projected to 000000H ~ 007FFFH for allowing reset
start and other vector addressing, or the lower 32KB of RAM
area which is projected to 008000H ~ 00FE7FH for allowing 0
page addressing of work RAM area. 

( 4)  “Expansion I/O” means expansion I/O device area which isad-

dressed to area other than page 0.

Fig. 5-2

•

ROM image area: Image is formed in ROM area address
C00000H to C07FFFH. This area is identical to IPL ROM area
which will beseparately developed. 

•

RAM image area: Image is formed in RAM area address 1F0000H
to 1F7E7FH. ( Note)  

Note:  Image can be formed in lower 32KB of RAS2.

Fig. 5-3

RESETS

STOP

CKDC8

RAS3

  4

  5

6

IC10B
74HC00S

/(RAS3./RESET)

/RESET

  1

  2

3

IC10A
74HC00S

VDD

C86
1000P

C87
1000P

R123

10K

C88
1000P

 9

10

8

14

IC10C
74HC00S

14

14

VDD

VDD

Internal I/O
External I/O
Memory image area

(*1)
(*2)
(*3)

RAM area
(10M byte)

ROM area
(3M byte)

Expansion I/O area (1M byte)

000000H

1C0000H

C00000H

FFFFFFH

000000H

004000H

008000H

00FFFFH

1FFFFFH

ROM image area
32KB

RAM image area
slightly smaller than32KB

NOT USE

00F800H

00FE80H

00FF80H

00FFFFH

RAM image area

Internal I/O area

External I/O area
(0 page)

1BFFFFH

RAM area

C00000H

D00000H

EFFFFFH

ROS3

NOT USE

  ROS1
(256K Byte)

C40000H

CA0000H

    ROS2
(Not used)

4 – 10

Fig. 5-4

Note:  RAS2 signal is formed as OR in the image area of 0 page.

(lower32KB).

Fig. 5-5

Note 1: MPCCS signal is the base signal for MPCA7 internal reg-

isterdecoding, and does not exist as an internal signal.

Note 2: OPCCS1 and OPCCS2 signals are decoded in the OPC

(optionperipheral controller) using the base signal OPTCS
for optiondecoding. They does not exist as external sig-
nals.

Fig. 5-6

Fig. 5-7

IPLON:  IPL board detection signal incorporated in the option slot.

Note used in the ER-A440. (Not used)

Access is performed with two ROM chip select signals ROS1 and
ROS2 , which decode 512KB address area respectively to access-
max. 4MB ROM. 

Fig. 5-8

Access is performed with two RAM chip select signals, RAS2 and
RAS3. The control register in MPCA7 allows selection of  pageimage
memory area. (RAS1 is selected for initializing.)

: For 0 page image area, selection between RAS2 and RAS3 can

bemade with the control register. The 0 page control registerper-
forms initializing at the timing of no stack processimmediately
after resetting. 

100000H

400000H

BFFFFFH

NOT USE

NOT USE

RAS1  (Not use)

RAS2  64K Byte

RAS3

512K Byte

1C0000H

1F0000H

200000H

(MAX 2MB)

280000H

(OPTION)

00FF80H

00FFA0H

00FFFFH

MPCCS

NOT USE

NOT USE

NOT USE

OPCCS1

OPCCS2

00FFC0H

00FFD0H

00FFE0H

00FFF0H

(*1)

(*2)

(*2)

00FFE8H

MCR1 (NOT USE)

MCR2 (NOT USE)

NOT USE

CPU

MPCA7

ROM1

(STANDARD)

RAM1
RAM2

(OPTION)

RAM

Data bus

Address bus

ROS1

RAS2

RAS3

Address

A23~A14

(IPLON)

Address
decorder

C80000H~CFFFFFH

C00000H~C7FFFFH

000000H~007FFFH

MPCA7

ROS2

ROS1

Address

A23~A14

Address
decorder

1C0000H~1DFFFFH

008000H~
 00F7FFH

*1

1E0000H~1FFFFFH

RAS1

RAS2

RESET

D

CK

Q

R

DOI

S8F

Control register

MPCA7

RAS3

200000H~3FFFFFH

4 – 11

This is the circuit employed to do the Special Service Preset(SSP). 

(Block diagram)

Fig. 6-1

(MPCA7 block diagram)

Fig. 6-2

As the address detection system, the brake address register compari-
son system is employed though the mapping system was employed
in the conventional monitor RAM. The address registerlocated in
MPCA is always compared with the system address bus to monitor
and generate NMI signal at a synchronized timing and togo to NMI
exception process. 
In the exception process routine service routine, the entry address is
checked to go to SSP sub routine. 
Entry to the break address register (BAR) is performed through ad-
dress FFFF00H or later decoded in MPCA7. 

The break address register (BAR) is accessed through direct address
of FFFF00H~FFFFFFH. Entry number is 32 entry.

Fig. 6-3

Each BAR is composed of 4 byte address. Bit composition is as
follows:

Fig. 6-4

 is the enable register. The entry registers of the break address are

assigned to 

, 

, and 

. Each bit of address corresponds to each

bit position, writing to 

, 

, and 

 is performed without shifting.

The corresponding area is 1MB space of ROS1 and ROS2.  

CPU

MPCA7

A0~23

D0~D7

NMI

SSPRQ

D0~

    D7

A23~

     A0

BAR  0

BAR  N

REGCS

Decode

Comparator

Coincide

Coincide

SPE

(Enable register)

SSPRQ

(NMI)

Control signal

ROMCS

O

N

1

2

3

4

FFFF00

H

1

2

3

4

5

6

7

BAR0

BAR1

BAR2

7

0

1

2

3

4

A19 A18 A17 A16 A15

A8

A7

A2

EN

Upper bits

Intermediate bits

Lower bits

Enable register
EN (bit7) = 1 Enable
               = 0 Inhibit

Don't care for "-----."

< BAR composition >

4 – 12

Access to SSP break address register is performed through the tem-
porary register as shown below:

Fig. 6-5

Enable flags can be accessed individually. 
Though enable register 

 can be accessed individually, writing to

brake address registers 

 and 

 is performed at the same time as

writing to brake address register 

 through the temporary register. 

Therefore, set 

 and 

 to temporary, then write into 

 at last. 

Since the temporary register is commonly used by BAR sets, thefol-
lowing register setting is performed after completion ofsetting of each
break address register. 

Access to the enable register and the brake address register is only
possible when writing to them from the CPU. 

Information on which brake register the SSP brake is detected in is
read as binary data by reading address FFFFFFH (*1). 
Used in an expanded register. 
Normally is a reserve bit. Whenreading, fixed to 0.
If there are 32 break registers, binary expression is made with the
above 5 bits, and 0th is “00000

B

” and 31st is “11111

B

.” 

When detected simultaneously by two or more break registers,
onewith the smaller BAR number is read as binary data. 
The brake signals (NMI) and the above detection data (CMP0~4)
areheld until the above detection data are read. So read should be-
made in the NMI sub routine. (Clear by FFFFFFH read.)

1: FFFFFFH is not fulldecoded. (FFFF00H~FFFFFFH). There-

fore,unnecessary read access in parentheses should not be
performed. 

1

2

3

4

A19 A18 A17 A16 A15

A8

A7

A2

EN

WR

WR

Temporary

Temporary

bit 7

6

5

4

3

2

1

0

0

0

CMP4

0

CMP3 CMP2 CMP1 CMP0 (FFFFFFH)

Fig. 7-1

The DP-730 is used as the R/J printer. The printer mechanical timing
control is made by the CPU through MPCA7. 

When the MTD is high, the motor rotates. 
When the MTD is low, the motor stops. 

CPU

Data
bus

MPCA7

DRIVER

PRINTER
(DP-730)

RECEIVER

Address bus

MTD

MPCA7

M

Speed limiter
circuit

2.2K

R128

+24V

C92

DP

Normal 555µs (516~590µs)

Main PWB side

Printer side

R127

COM

Q7

C227

MTD

DP

4 – 13