Sharp XL-UR5H (serv.man2) Service Manual ▷ View online
XL-UR5H
8 – 10
IC902 92L31000925900 : MOTOR DRIVER ( SC9259 )
Figure 8-7 BLOCK DIAGRAM OF IC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
1
2
3
4
5
6
7
8
9 10 11 12 13 14
21 20 19 18 17 16 15
28 27 26 25 24 23 22
FIN (GND)
MUTE
REO
REB
VIFC2
VIFC1
VOFC2
VOFC1
V
CC2
VREF
VITK1
VITK2
VOTK1
VOTK2
GND3
VILD2
GND2
VOSP2
VOSP1
VISP
VILD1
GND1
VOLD1
VOLD2
VOSL1
VOSL2
VISL
LD CTL
V
CC1
FIN (GND)
SA9259
TSD
28
27
26
25
24
23
22
21
20
19
18
17
16
15
LEVER CONVERSION
BUFFER
10K
10K
10K
10K
10K
50K
2.5V
50K
10K
+
+
+
+
LEVER CONVERSION
BUFFER
10K
10K
+
+
LEVER CONVERSION
BUFFER
LEVER CONVERSION
BUFFER
LEVER CONVERSION
BUFFER
Voltage Regulatory
MUTE
+
10K
10K
XL-UR5H
8 – 11
IC903 92L31000961800 : CD RF ( SA9618 )
Figure 8-8 BLOCK DIAGRAM OF IC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
LDON
AGC
RFRC
RFI
RFO
RFM
NC
VTH
LD
MON
PD1
PD2
GND
VREF
NC
SA9618/SA9618A
1
3
14
12
4
5
9
8
15
2
6
13
16
11
10
7
10K
PD2
2K
2K
30K
30K
2K
6P
VREF
VREF
VREF
VREF
RFI
AGC
VTH
MON
VREF
8K
+
+
10K
2K
6K
54K
55K
3.4K
1.24V
10K
6P
VREF
8K
12K
10K
+
+
+
+
+
+
+
VREF
VREF
RFM
RFO
V
DD
RFRC
GND
LD
LDON
NC
NC
+
+
Mode
SW
10K
55K
55K
VL
+
XL-UR5H
8 – 12
U2 92L31003980031 : FLASH MEMORY ( SST39VF800A )
Figure 8-9 BLOCK DIAGRAM OF IC
PIN DESCRIPTION
SST39LF / VF800A
A15
A14
A13
A12
A11
A10
A18
A17
A9
A7
A6
A5
A4
A3
A1
A2
A8
NC
NC
NC
NC
NC
NC
WE#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
0E#
CE#
A0
DQ8
DQ0
DQ9
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
NC
V SS
V SS
V DD
Memory Address
Address Buffer & Latches
X-Decoder
SuperFlash
Memory
Y-Decoder
I/O Buffers and Data Latches
DQ
CE#
OE#
WE#
Control Logic
15
DQ
O
-
Symbol
Pin Name
Functions
A
Address Inputs
To provide memory addresses. During Sector-Erase address lines will select the
A
MS
DD
0
1
A
Most significant address
=
MS
A
for SST39LF/VF200A,
=
MS
A
16
for SST39LF/VF400A, and
A
17
for SST39LF/VF800A
A
18
-
-
A
A
MS
11
-
A
A
MS 15
-
sector. During Block-Erase address lines will select the block.
DQ
Data Input/output
To ouput data during Read cycles and receive input data during Write cycles.
CE#
Chip Enable
To activate the device when CE# is low.
OE#
Output Enable
To gate the data output buffers.
NC
No Connection
Unconnected pins.
WE#
Write Enable
To control the Write operations.
V
Power Supply
To provide power supply voltage:
SS
V
Ground
DQ
15
0
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.
The outputs are in tri-state when OE# or CE# is high.
3.0-3.6V for SST39LF200A/400A/800A
2.7-3.6V for SST39VF200A/400A/800A
2.7-3.6V for SST39VF200A/400A/800A
1.
XL-UR5H
8 – 13
IC201 92L21000330800 BA3308 (DUAL PRE-AMPLIFIER)
BLOCK DIAGRAM
Figure 8-10 BLOCK DIAGRAM OF IC
IC701 92L31000409400 CD74HC4094 (8-STAGE SHIFT AND STORE BUS REGISTER)
BLOCK DIAGRAM
Figure 8-11 BLOCK DIAGRAM OF IC
MUTE
ALC
ch2
ch1
-
+
-
+
1
2
3
4
5
6
7
8
9
NF1
NF2
INPUT1
INPUT2
OUTPUT1
OUTPUT2
GND
ALC
V
CC
VDD
OE
Q5
Q6
Q7
Q8
NC
NC
GND
SCL
SDA
STR
Q4
Q3
Q2
Q1
16
1
2
3
4
5
6
7
8
15
14
13
12
11
10
9
IC701 74HC4094
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