Sharp XL-UR5H (serv.man2) Service Manual ▷ View online
XL-UR5H
8 – 6
IC501 92L31000731400 : VOLUME CONTROLLER ( SC7314 )
Figure 8-4 BLOCK DIAGRAM OF IC
1
V
DD
2
GND
3
L
4
R
5
IN (R)
6
OUT
(R)
7
LOUD (R)
8
R4
9
R3
10
R2
11
R1
12
LOUD (L)
13
L4
14
L3
28
CREF
27
SCL
26
SDA
25
DIF GND
24
OUT
(L)
23
OUT
(R)
22
BOUT
(R)
21
BIN (R)
20
BOUT
(L)
19
BIN (L)
18
OUT
(L)
17
IN (L)
16
L1
15
L2
SC7314
18
OUT
(L)
17
IN
(L)
12
LOUDNESS
(L)
20
B-OUT
(L)
19
B-IN
(L)
3
TREBLE
(L)
6
OUT
(R)
1
8
9
10
11
28
V
DD
2
GND
5
IN
(R)
7
LOUDNESS
(R)
22
13
14
15
16
B-OUT
(R)
21
23 Rout
25 GND
26 SDA
27 SCL
24 Lout
B-IN
(R)
4
TREBLE
(R)
I
2
C BUS Decode + Data Storage Lock
Vol Control
Vcc
C
REF
Input selector
Gain control
Gain control
Input selector
Gain control
Gain control
L
channel input
Bass
Control
Treble
Control
Vol Control
Bass
Control
Treble
Control
Audio
OUTPUT
Mute
Audio
OUTPUT
Mute
R channel input
XL-UR5H
8 – 7
IC705 92L31000162202 : LCD CONTROLLER ( HT1622BD ) ( 1/2 )
Figure 8-5 BLOCK DIAGRAM OF IC
HT1622
CS
1
NC
2
RD
3
WR
4
DATA
5
VSS
6
OSCI
7
VDD
8
VLCD
9
IRQ
10
BZ
11
NC
12
BZ
13
T1
14
T2
15
T3
16
COM0
17
COM1
18
NC
19
NC
51
NC
50
NC
49
SEG19
48
SEG18
47
SEG17
46
SEG16
45
SEG15
44
SEG14
43
SEG13
42
SEG12
41
SEG11
40
SEG10
39
SEG31
64
SEG30
63
SEG29
62
SEG28
61
SEG27
60
SEG26
59
SEG25
58
SEG24
57
SEG23
56
SEG22
55
SEG21
54
SEG20
53
NC
52
COM2
20
COM3
21
COM4
22
COM5
23
COM6
24
COM7
25
SEG0
26
SEG1
27
SEG2
28
SEG3
29
SEG4
30
SEG5
31
SEG6
32
SEG9
38
SEG8
37
SEG7
36
NC
35
NC
34
NC
33
OSCI
CS
RD
BZ
WR
VDD
VSS
BZ
DATA
Tone Frequency
Generator
IRQ
VLCD
SEG31
SEG0
COM7
COM0
Watch Dog Timer
&
Time Base Generator
Control
&
Timing
Circuit
Display RAM
LCD Driver/
Bias Circuit
XL-UR5H
8 – 8
IC705 92L31000162202 : LCD CONTROLLER ( HT1622BD ) ( 2/2 )
PIN DESCRIPTION
Pad No.
Pad Name
I/O
Description
1
CS
Input
Chip selection input with pull high resistor. When the CS is logic high, the data
and command read from or written to the HT1622 are disabled. The serial inter-
face circuit is also reset. But if the CS is at a logic low level and is input to the
CS pad, the data and command transmission between the host controller and
the HT1622.
and command read from or written to the HT1622 are disabled. The serial inter-
face circuit is also reset. But if the CS is at a logic low level and is input to the
CS pad, the data and command transmission between the host controller and
the HT1622.
2
RD
Input
READ clock input with pull high resistor. Data in the RAM of the HT1622 are
clocked out on the rising edge of the RD signal. The clocked out data will
appear on the data line. The host controller can use the next falling edge to
latch the clocked out data.
clocked out on the rising edge of the RD signal. The clocked out data will
appear on the data line. The host controller can use the next falling edge to
latch the clocked out data.
3
WR
Input
WRITE clock input with a pull high resisitor. Data on the DATA line are latched
into the HT1622 on the rising edge of the WR signal.
into the HT1622 on the rising edge of the WR signal.
4
DATA
Input/Output
Serial data input/output with a pull high resistor.
5
VSS
Input
Negative power supply. Ground.
6
OSCI
Input
If the system clock comes from an external clock source, the external clock
source should be connected to the OSCI pad.
source should be connected to the OSCI pad.
7
VDD
Input
Positive power supply.
8
VLCD
Input
LCD operating voltage input pad.
9
IRQ
Output
Time base or Watch Dog Timer overflow flag, NMOS open drain output.
10, 11
BZ, BZ
Output
2K or 4K frequency output pair.
12 - 14
T1 - T3
Input
Not connected.
15 - 22
COM0 - COM7
Output
LCD common outputs.
23 - 54
SEG0 - SEG31
Output
LCD segment outputs.
XL-UR5H
8 – 9
IC901 92L31000964100 : CD SERVO ( SC9641 )
Figure 8-6 BLOCK DIAGRAM OF IC
48
49
CR
R
VREF
VDD0
VSS0
VDDA
RESET
TESR
IO.0
IO.1
IO.2
IO.3
IO.4
IO.5
IO.6
IO.7
ACK
STB
DATA
CL16
MCLK_IN
NC
DATA_IN
SCLK_IN
WCLK_IN
DATA_OUT
SCLK_OUT
WCLK_OUT
MUTE
MODE
CROUT
CRIN
VDDA2
VSSA2
RFREF
RFIN
Idata
Va
d
c
VCOM
E
F
D
C
A
B
VDDA1
V
A
AA1
lr
ERR
CL
L
RAD
FOC
SLED
VSSP
NC
MOTO
VDDP
GND
TRAY_SW
SLED_SW
LDON
V
DD
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
47
46
45
44
43
42
SC9641
41
40
39
38
37
36
35
34
33
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
BCLK
4
A
B
C
D
E
B
C
D
E
F
VCOM
Vadc
Idata
RFIN
RFREF
MOTO
lr
3
5
6
8
7
9
10
11
12
13
14
58
LDON
64
CRIN
17
CROUT
CL
16
L
CL
CR
R
VREF
MCLK_IN
ERR
DATA_OUT
SCLK_OUT
WCLK_OUT
RESET
TEST
TRAY_SW
TEST
TRAY_SW
SLED_SW
ACK
STB
DATA
STB
DATA
WCLK_IN
SCLK_IN
DATA_IN
Clock
control
Digital Signal
Processor
Decode
Audio D/A
Microcomputer
Connector
Servo signal
Processor
Analog
and
Digital
Conversion
Conversion
18
30
51 50 49 48 47
29
24
23
22
21
63
62
42
43
31
32
33
25
26
27
41
40
39
38
37
36
35
34
54
53
52
IO.0
IO.1
SLED
FOC
RAD
IO.2
IO.3
IO.4
IO.5
IO.6
IO.7
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