Sharp XL-UR5H (serv.man2) Service Manual ▷ View online
XL-UR5H
8 – 2
U5 92L31000250100 : CPU ( TS2501 ) ( 1/4 )
Figure 8-2 BLOCK DIAGRAM OF IC
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
17
70
69
68
67
66
65
GPIO_D21
GPIO_D20
GPIO_D19
GPIO_D18
GPIO_D17
GPIO_D16
GPIO_D15
PKG1
VSSI_ADC
VDDI_ADC
VBBA_ADC
VSSA_ADC
ADIN4
ADIN2
ADIN0
VDDA_ADC
VBBA_PLL
VSSA_PLL
XFIL
T
VDDA_PLL
VDDIO
XOUT
XIN
READY
nRESET
VDD_OSC
XT
OUT
XTIN
DAI/GPIO_B25
DAO/GPIO_B24
MCLK/GPIO_B23
VSSIO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VSSIO
XD4
XD5
XD6
XD7
XD8
VDDI
VSSI
XD9
XD10
XD1
1
XD12
XD13
XD14
XD15
VDDIO
XA0
XA1
XA2
XA3
XA4
XA5
XA6
VDDI
VSS1
XA7
XA8
XA9
XA10
XA1
1
XA12
VSSIO
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
113
114
115
116
116
117
118
119
119
120
121
122
123
124
124
126
127
128
VSSIO
MODE1
TDI
TMS
TCK
TDO
nTRST
SDO0/GPIO_A0
SCK0/GPIO_A1
SFRM0/GPIO_A2
SDI0/GPIO_A3
SDO1/GPIO_A4
VDDI
VSSI
SCK1/GPIO_A5
VDDIO
SFRM1/GPIO_A5
SDI1/GPIO_A7
SDO2/GPIO_A8
SCK2/GPIO_A9
SFRM2/GPIO_A10
SD12/GPIO_A11
VDDI
VSSI
EXINT0/GPIO_A12
EXINT1/GPIO_A13
EXINT2/GPIO_A14
EXINT3/GPIO_A15
XDD
XD1
XD2
XD3
64
63
62
61
60
59
58
57
57
56
55
54
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
33
VDD-USB
LRCK/GPIO_B22
BCLK/GPIO_B21
UT_RX/IDE_nCS/GPIO_59
UT_TX/GPIO_88
nOE
nWE
ND_nWE/GPIO_B7
ND_nWE/GPIO_B7
SD_CKE/GPIO_B0
VSSI
USBH_CN/GPIO_B29
USBH_DP/GPIO_B28
USB_DN/GPIO_B27
USB_DP/GPIO_B26
nCS3/nOE3/GPIO_B5
nCS/nOE2/GPIO_B4
nCS1/nOE1/GPIO_B3
nCS0/nOE0/GPIO_B2
SD_nCS/GPIO_B1
VSSIO
SD_CLK/GPO
XA21/DQM0
XA20/DQM1
VDD1
XA19
XA18
XA17/CLE
XA16/nRAS/ALE
XA15/nCAS
XA14/BA1
XA13/BA0
VDDIO
VDDIO
Ts2501
XL-UR5H
8 – 3
U5 92L31000250100 : CPU ( TS2501 ) ( 2/4 )
Figure 8-3 BLOCK DIAGRAM OF IC
USB_DP/GPIO_B[28], USB_DN/GPIO_B[27]
XIN, XOUT
XFILT
XTIN, XTOUT
TCO2/GPIO_A[11]
TCO5/GPIO_A[8]
TCO1/GPIO_A[7]
TCO4/GPIO_A[4]
TCO0/GPIO_A[3]
TCO3/GPIO_A[0]
EXINT[3:0] /
GPIO_A[15:12]
GPIO_A[15:12]
GPIO_A[11:0]
GPIO_A[15:0]
GPIO_B[20:21]
GPIO_B[9:7]
GPIO_B[5:0]
GPIO_D[17:15]
GPIO_B[9:7]
GPIO_B[5:0]
GPIO_D[17:15]
UT TX/GPIO_B[8]
UT RX/GPIO_B[8]
UT RX/GPIO_B[8]
GPIO_A[11:10]
DAO / GPIO_B[24]
MCLK / GPIO_B[23]
BCLK / GPIO_B[21]
LRCKO / GPIO_B[22]
DAI / GPIO_B[25]
GPIO_A[3] / CDAI
GPIO_A[2] / CLRCK
GPIO_A[1] / CBCLK
GPIO_A[2] / CLRCK
GPIO_A[1] / CBCLK
GPIO_D[21:15]
GPIO_A[3:0]
TDI. TMS. TCK
nTRST, TDO
DQM[0:1] / XA[21:20]
DQS[1:0] / XA[19:18]
ND_CLE / XA[17]
ND_ALE / SD_nRAS / XA[16]
SD_nCAS / XA[15]
SD_BA[1:0] / XA[14:13]
XA[12:0]
XD[15:0]
nOE. nWE. nCS[3:0]
SD_nCS, SD_CKE
SD_CLK
ND_nWE
IDE_nCS1
READY
GPIO_A[9:8]
GPIO_D[17:16]
GPIO_D[17:16]
ADIN0
ADIN1
ADIN4
ADIN1
ADIN4
ADC
12C
UART/IrDA
GPIO
GSIO
Interrupt
Controller
Timers/
Counters
Pll &
CLK Generator
USB1.1
Host/Device
ECC
Generation
APB
Bridge
AHB Arbiter
DMA
(2-channel)
Video Input
Interface
JTAG
ARM940T
AHB Wrapper
Ext. Memory
Interface
SRAM
(64KB)
Boot ROM
(4KB)
DAI (12S)
for
CODEC
&
CD-DSP
USBH_DP/GPIO_B[28], USBH_DN/GPIO_B[29]
XL-UR5H
8 – 4
U5 92L31000250100 : CPU ( TS2501 ) ( 3/4 )
PIN DESCRIPTION
PIN DESCRIPTION
Signal Name
Shared Signal
Pin #
Type
Description-TS2501
External Memory Interface Pins
SD_CKE
GPIO_B[0]
56
Input/Output
SDRAM Clock Enable signal. Active high. / GPIO_B[0]
SD_CLK
GPO
44
Input/Output
SDRAM Clock / GPO. SD_CLK can be used as a general purpose output.
Refer to section “MEMORY CONTROLLER”.
(MCFG register Bit[3] and Bit [1])
Refer to section “MEMORY CONTROLLER”.
(MCFG register Bit[3] and Bit [1])
SD_nCS
SD_nCLK/
GPIO_B[1]
GPIO_B[1]
46
Input/Output
Chip select signal for SDRAM, Active low / Inverted SD_CLK for DDR
SDRAM / GPIO_B[1]
SDRAM / GPIO_B[1]
XA[21:20]
DQM[0:1]
43:42
Input/Output
External Bus Address Bit [21:20] / Data I/O Mask 0, 1
XA[19:18]
DQS[1:0]
40:39
Input/Output
External Bus Address Bit [19:18] / DDR SDRAM / GPIO_B[1]
XA[17]
ND_CLE
38
Input/Output
External Bus Address Bit [17] / CLE for NAND Flash
XA[16]
SD_nRAS
37
Input/Output
External Bus Address Bit [16] / SDRAM RAS signal / ALE for NAND Flash
XA[15]
SD_nCAS
36
Input/Output
External Bus Address Bit [15] / SDRAM CAS signal
XA[14]
SD_BA[1]
35
Input/Output
External Bus Address Bit [14] / SDRAM Bank Address 1
XA[13]
SD_BA[0]
34
Input/Output
External Bus Address Bit [13] / SDRAM Bank Address 0
XA[12:7]
31:26
Input/Output
External Bus Address Bit [12:0]
XA[6:0]
23:17
XA[15:9]
15:9
Input/Output
External Bus Address Bit [15:0]
XA[8:4]
6:2
XA[3:0]
128:125
NCS[3:0]
ND_nOE[3:0] /
GPIO_B[5:2]
GPIO_B[5:2]
50:47
Input/Output
External Bus Chip Select [3:0] / NAND Flash Output Enable [3:0] /
GPIO_B[5:2]
GPIO_B[5:2]
ND_nWE
GPIO_B[7]
57
Input/Output
NAND Flash WE. Active low. / GPIO_B[7]
nWE
58
Input/Output
Static Memory Write Enable signal. Active low.
nOE
59
Input/Output
Static Memory Write Output Enable signal. Active low.
READY
73
Input
Ready information from external device.
SDRAM / Inverted Clock for DDR SDRAM.
SDRAM / Inverted Clock for DDR SDRAM.
GPIO_B[0]
SD_CKE
56
Input/Output
GPIO[0] / SDRAM clock control
GPIO_D[21:1
8]
8]
FGPIO[14:11] /
CISD[7:4]
CISD[7:4]
96:93
Input/Output
GPIO_D[21:18] / Fast GPIO bits 14 ~ 11 / Camera Interface Data Inputs
3 ~ 0. Internal pull-up resistors are enabled at reset. GPIO_D[19:18] are
disabled in TS250IT(N.C).
3 ~ 0. Internal pull-up resistors are enabled at reset. GPIO_D[19:18] are
disabled in TS250IT(N.C).
GPIO_D[17]
FGPIO[10] / SCL
/ CISHS
/ CISHS
92
Input/Output
GPIO_D[17] / Fast GPIO bit 10 / 12C SCL / Camera Interface Hsync.
GPIO_D[16]
FGPIO[9] / SDA /
CISVS
CISVS
91
Input/Output
GPIO_D[16] / Fast GPIO bit 9 / 12C SDA / Camera Interface Vsync.
GPIO_D[15]
FGPIO[9] /
CISCLK
CISCLK
90
Input/Output
GPIO_D[15] / Fast GPIO bit 8 / Camera Interface Clock
ADC Input Pins
ADIN_0
-
82
Audio Input
General purpose multi-channel ADC input 0
ADIN_2
-
83
Audio Input
General purpose multi-channel ADC input 2
ADIN_4
-
84
Audio Input
General purpose multi-channel ADC input 4
Clock Pins
XIN
-
74
Input
Main Crystal Oscillator Input for PLL. 12MHz Crystal must be used if USB
Boot Mode is required. Input voltage must not exceed VDD_OSC
(1.95V max).
Boot Mode is required. Input voltage must not exceed VDD_OSC
(1.95V max).
XOUT
-
75
Output
Main Crystal Oscillator Output for PLL
XFILT
-
78
Audio Output
PLL filter output
XTIN
-
69
Input
Sub Crystal Oscillator Input. 32.768kHz is recommended. Input voltage
must not exceed VDD_OSC (1.95V max).
must not exceed VDD_OSC (1.95V max).
XTOUT
-
70
Output
Sub Crystal Oscillator Output
Mode Control Pins
MODE1
-
98
Input
Mode Setting Input 1. Pull-down for normal operation.
PKG1
-
89
Input
Package ID1. Pull-up for normal operation.
nRESET
-
72
Input
System Reset. Active low.
JTAG Interface Pins
TDI
-
99
Input
JTAG serial data input for ARM940T
TMS
-
100
Input
JTAG test mode select for ARM940T
TCK
-
101
Input
JTAG test clock for ARM940T
TDO
-
102
Input/Output
JTAG serial data output for ARM940T. External pull-up resistor is required
to prevent floating during normal operation.
to prevent floating during normal operation.
nTRST
-
103
Input
JTAG reset signal for ARM940T. Active low.
XL-UR5H
8 – 5
Power Pins
VDDIO
-
112
76
33
16
76
33
16
POWER
Digital Power for I/O (1.8V ~ 3.3V)
VDD_USB
-
64
POWER
Power for USB I/O (3.3V)
VDD_OSC
-
71
POWER
Digital Power for Oscillators (1.8V)
VDDI
-
119
109
41
24
7
109
41
24
7
POWER
Digital Power for Internal Core (1.8V)
VDDI_ADC
-
87
POWER
Digital Power for ADC (1.8V)
VDDA_ADC
-
81
POWER
Analog Power for ADC (3.3V)
VDDA_PLL
-
77
POWER
Analog & Digital Power for PLL (1.8V)
VSSIO
-
97
65
45
32
1
65
45
32
1
GROUND
Digital Ground for I/O
VSSI
-
120
110
55
25
8
110
55
25
8
GROUND
Digital Ground for Internal
VSSI_ADC
-
88
GROUND
Digital Ground for ADC
VBBA_ADC
-
86
GROUND
Analog Ground for ADC
VSSA_ADC
-
85
GROUND
Analog Ground for ADC
VBBA_PLL
-
80
GROUND
Analog Ground for PLL
VSSA_PLL
-
79
GROUND
Analog Ground for PLL
Signal Name
Shared Signal
Pin #
Type
Description-TS2501
U5 92L31000250100 : CPU ( TS2501 ) ( 4/4 )
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