Sharp SM-SX100 (serv.man2) Service Manual ▷ View online
SM-SX100
– 57 –
IC901~IC903 VHiBU2114F+-1: LED Driver (BU2114F)
• Outline
It is the low power consuming CMOSIC which has the latch in the 8-bit shift register and can asynchronously latch the data latched
in the shift register. Since the output (O1 to O8) is the open drain output (Since the protective diode is not provided, the voltage
of VDD or more to max. 7V is applicable, and the drive is possible at 36mA per output up to the total output of 150mA. (Static
operation mode)
It is the low power consuming CMOSIC which has the latch in the 8-bit shift register and can asynchronously latch the data latched
in the shift register. Since the output (O1 to O8) is the open drain output (Since the protective diode is not provided, the voltage
of VDD or more to max. 7V is applicable, and the drive is possible at 36mA per output up to the total output of 150mA. (Static
operation mode)
1
SIN
Input
Serial data input terminal
2
CK
Input
Shift clock of shift register
3
LATCH
Input
When the terminal is turned to "L", the latch output is held.
Moreover, the latch output also varies as the shift register output varies when it is "H".
Moreover, the latch output also varies as the shift register output varies when it is "H".
4*
SOUT
Output
Output of shift register of the final step
5
EN
Input
Enable terminal of O1 to O8
When the terminal is "L", the latch output appears as it is.
However, the output Qn is "L" when the latch output is "H", and Qn is "hi-Z" when the latch
output is "L".
When the terminal is "L", the latch output appears as it is.
However, the output Qn is "L" when the latch output is "H", and Qn is "hi-Z" when the latch
output is "L".
6
RST
Input
Shift register, latch reset
7 - 9
GND
—
0V Power supply
10
O8
Output
Latch output at 8th step of shift register
11
O7
Output
Latch output at 7th step of shift register
12
O6
Output
Latch output at 6th step of shift register
13
O5
Output
Latch output at 5th step of shift register
14
O4
Output
Latch output at 4th step of shift register
15
O3
Output
Latch output at 3rd step of shift register
16
O2
Output
Latch output at 2nd step of shift register
17
O1
Output
Latch output at 1st step of shift register
18
VDD
—
+VDD power supply
Pin No.
Port Name
Input/Output
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Note) Output of O1 to O8 is an open-drain type, and when the output of the shift register is "H", the output becomes the level "L".
Note) Output of O1 to O8 is an open-drain type, and when the output of the shift register is "H", the output becomes the level "L".
Function
SIN
CK
LATCH
SOUT
EN
RST
GND
GND
GND
V
DD
01
02
03
04
05
06
07
08
Figure 57 BLOCK DIAGRAM OF IC
SM-SX100
– 58 –
IC904 RH-iX2816AFZZ: System Microcomputer (IX2816AF)
1
LED3, P83
DATA_IN
Input
External IC communication input
2
LED2, P82
DATA_OUT
Output
External IC communication output
3
LED1, P81
IC_CLK
Input
External IC communication clock
4
LED0, P80
—
Input
Not used
5
AN0, PA0
KEY
Input
Key input. A/D input. VER.1
6
AN1, PA1
VOL DIS
Input
A/D input to display VOL value
7
AN2, PA2
KEYA
Input
Key input. A/D input. VER.2
8
AN3, PA3
KEYB
Input
Key input. A/D input. VER.2
9
AN4, PA4
KEYC
Input
Key input. A/D input. VER.2
10-12
AN5, PA5-AN7, PA7
—
Input
Not used
13
VDD
VDD
—
Power supply
14
OSC2
OSC2
Output
Oscillator
15
OSC1
OSC1
Input
Oscillator
16
VSS
VSS
—
Power supply
17*
NC
—
—
Not used
18
TXD, SBD0, P00
SDATA
Outout
Output to serial/parallel converter for LED display. DATA
19
RXD, SBI0, P01
SLATCH
Outout
Output to serial/parallel converter for LED display. Latch output
20
SBT0, P02
SCLK
Output
Output to serial/parallel converter for LED display. Clock output
21
BUZZER, P06
IC_RESET
Output
Reset output to external IC
22*
RMOUT, P10
AUD MUTE
Output
Output for AUDIO MUTE
23*
P11
CL_CONT
Output
Clock control between external IC and IC
24
P12, TMIO2
DCLK
Output
Setting output to D/A. Clock output
25
P13, TMIO3
DLATCH
Output
Setting output to D/A. Latch output
26
P14, TMIO4
DDATA
Input/Output Setting output to D/A. Data input/output
27
P20, IRQ0
PROTECT
Input
PROTECT signal detection input
28
P21, IRQ1, SENS
P-IN
Input
Warning input
29
P22, IRQ2
IC_STB
Input
External IC communication strobe
30
P60
DIG_B
Output
Digital input switch B
Switch of digital input is controlled with DIG_A and B.
Switch of digital input is controlled with DIG_A and B.
31
P61
DIG_A
Output
Digital input switch A
32
P62
DIG_MUTE
Output
Output for digital mute
33
P63
AUX3
Output
Input relay of AUX3 is switched.
34
P64
AUX2
Output
Input relay of AUX2 is switched.
35
P65
AUX1
Output
Input relay of AUX1 is switched.
36
P66
AMP DIG
Output
Input (digital, analog) to AMP is switched.
37*
P67
AMP ANA
Output
Input (digital, analog) to AMP is switched.
38
P70
DIG_C
Output
Digital input switch C
Switch of digital input accompanied to AUX1 is controlled.
Switch of digital input accompanied to AUX1 is controlled.
39
P27, NRST
RESET
Input
Reset
40
MMOD
TEST
—
TEST
41
P87, LED7
SP_RLY
Output
ON/OFF of speaker relay
42
P86, LED6
POWER
Output
Control terminal of power supply
43
P85, LED5
LINE_MUTE
Output
Line mute for recording
44
P84, LED4
WAR_OUT
Output
Warning output
Port Name
Terminal Name
Pin No.
Input/Output
Function
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
SM-SX100
– 59 –
IC904 RH-iX2816AFZZ: System Microcomputer (IX2816AF)
Figure 59-1 BLOCK DIAGRAM OF IC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
33
32
31
30
29
28
27
26
25
24
23
44
43
42
41
40
39
38
37
36
35
34
MN101C117ßF
LED3,P83
LED2,P82
LED1,P81
LED0,P80
AN0,PA0
AN1,PA1
AN2,PA2
AN3,PA3
AN4,PA4
AN5,PA5
AN6,PA6
DATA-IN
DATA-OUT
IC_CLK
KEY
VOLDIS
KEYA
KEYB
KEYC
P63
P62
P61
P60
P22,IRQ2
P21,IRQ1,SENS
P20,IRQ0
P14,TM4IO
P13,TM3IO
P12,TM2IO
P11
AN7,PA7
VDD
OSC2
OSC1
VSS
NC
TXD,SBO0,P00
RXD,SBI0,P01
SBT0,P02
BUZZER,P06
RMOUT,P10
P84,LED4
P85,LED5
P86,LED6
P87,LED7
MMOD
P27,NRST
P70
P67
P66
P65
P64
WAR_OUT
LINE_MUTE
POWER
SP_RLY
RESET
DIG_C
AMP ANA
AMP DIG
AUX1
AUX2
AUX3
DIG_MUTE
DIG_A
DIG_B
IC_STB
P_IN
PROTECT
D DATA
D LATCH
D CLK
CL_CONT
VDD
OSC2
OSC1
VSS
SDATA
SLATCH
SCLK
IC_RESET
AUD MUTE
Pin No.
Terminal Name
Function
1
VDD
Positive Supply to lower gate drivers. De-couple this pin to Vss (pin 7).
Bootstrap diode connected to HB (pin 2).
Bootstrap diode connected to HB (pin 2).
2
HB
High-Side Bootstrap supply. External bootstrap capacitor is required.
Connect positive side of bootstrap capacitor to this pin. Bootstrap diode is on-chip.
Connect positive side of bootstrap capacitor to this pin. Bootstrap diode is on-chip.
3
MO
High-Side Output. Connect to gate of High-Side power MOSFET.
4
HS
High-Side Source connection. Connect to source of High-Side power MOSFET.
Connect negative side of bootstrap capacitor to this pin.
Connect negative side of bootstrap capacitor to this pin.
5
HI
High-Side input.
6
LI
Low-Side input.
7
Vss
Chip negative supply, generally will be ground.
8
LO
Low-Side Output. Connect to gate of Low-Side power MOSFET.
ICA4~ICA7 VHiHiP2100/-1: FET Driver (HIP2100)
Figure 59-2 BLOCK DIAGRAM OF IC
1
2
2
3
4
8
7
7
6
5
VDD
HB
HO
HS
LO
VSS
LI
HI
1
8
4
3
2
5
6
7
VDD
HI
LI
VSS
LO
HS
HO
HB
UNDER
VOLTAGE
UNDER
VOLTAGE
LEVEL SHIFT
DRIVER
DRIVER
SM-SX100
– 60 –
ICA1 RH-iX2815AFZZ: 7TH ORDER MODULATION CONVERSION LSI (IX2815AF)
1
VDDR
—
R channel digital output section power terminal
2
OUTR (+)
Output
R channel forward output terminal
3
OUTR (–)
Output
R channel reverse output terminal
4
GNDD
—
Digital output section ground terminal
5
OUTL (–)
Output
L channel reverse output terminal
6
OUTL (+)
Output
L channel forward output terminal
7
VDDL
—
L channel digital output section power terminal
8
VDDX
—
Oscillation section power terminal
9
XI
Input
Quartz oscillator connection terminal. Clock necessary for the system is generated.
10
XO
Output
Quartz oscillator connection terminal. Clock necessary for the system is generated.
11
GNDX
—
Oscillation section ground terminal
12*
MCK
Output
System clock output terminal
13
TEST
Input
Test terminal. As usual, it is used at "L".
14
NFL1 (+)
Input
L channel forward signal feedback input terminal
15
NFL2 (–)
Input
L channel reverse signal feedback input terminal
16
GNDA
—
Analog ground terminal for AD converter
17
Lch IN
Input
L channel analog input terminal
18
Lch Vref
—
Reference voltage terminal for L channel
19
Rch Vref
—
Reference voltage terminal for R channel
20
Rch IN
Input
R channel analog input terminal
21
RESET
Input
Reset terminal. It is reset with "L".
22
NFR2 (–)
Input
R channel reverse signal feedback input terminal
23
NFR1 (+)
Input
R channel forward signal feedback input terminal
24
VDDA
—
Analog current terminal for AD converter
Pin No.
Port Name
Input/Output
Function
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VDDR
VDDA
NFR1(+)
NFR2(–)
RESET
Rch IN
Rch Vref
Lch Vref
Lch IN
GNDA
NFL2(–)
NFL1(+)
TEST
OUTR(+)
OUTR(–)
GNDD
OUTL(–)
OUTL(+)
VDDL
VDDX
XI
XO
GNDX
MCK
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VDA
NFR1(+)
NFR2(–)
RESET
Rch IN
Rch Vre
f
Lch Vref
Lch IN
GNDA
NFL2(–)
NFL1(+)
TEST
VDDR
OUTR(+)
OUTR(–)
GNDD
OUTL(–)
OUTL(+)
VDDL
VDDX
XI
XO
GNDX
MCK
Lch 7th order
Modulation Circuit
Rch 7th order
Modulation Circuit
Comparator
Comparator
Amplitude Doubling
Converter
Amplitude Doubling
Converter
Oscillator
Figure 60 BLOCK DIAGRAM OF IC
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