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– 53 –

1, 2

DI

Input with pull-up resistor

Input data

3, 4

BCKI

Input with pull-up resistor

Bit clock on the input side

5

LRCI

Input with pull-up resistor

Word clock on the input side

6

ICLK

Input

System clock input on the input side

7

ICKSL

Input with pull-up resistor

System clock on the input side (ICLK) selection. H:384fsi, L: 256fsi

Input format setting at IFM1 and IFM2

8*, 9*

IFM1

Input with pull-up resistor

10, 11

IFM2

Input with pull-up resistor

12, 13

VDD

—

Power supply terminal (5V)

14, 15

DMUTE

Input with pull-up resistor

(Direct) mute

16

MCOM

Input with pull-up resistor

Function switch of 17 to 20 pins

17

MDT/FSI1

Input with pull-up resistor

In case of MCOM=H, Microcomputer data input: MDT
In case of MCOM=L, De-emphasis frequency setting: FSI1

In case of MCOM=H, Bit-clock for microcomputer data input: MCK
In case of MCOM=L, De-emphasis frequency setting :FSI2

18

MCK/FSI2

Input with pull-up resistor

19, 20

MLEN/DEEM

Input with pull-up resistor

In case of MCOM=H, Microcomputer data word latch clock: MLEN
In case of MCOM=L, De-emphasis ON/OFF control: DEEM

Output format setting with OW18N, OW20N

21, 22

OW18N

Input with pull-up resistor

23, 24

OW20N

Input with pull-up resistor

25, 26

IISN

Input with pull-up resistor

IIS output mode selection. H: Normal mode, L: IIS mode

27*

STATE

Output

Output to express the internal operational state (for operation check)

28*

TST1N

Input with pull-up resistor

Control of output dither. H: Dither OFF, L: Dither ON

29*

TST2N

Input with pull-up resistor

Test terminal. Set at H.

30, 31

RSTN

Input with pull-up resistor

Reset terminal

32, 33

Vss

—

GND terminal (0V)

In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.

• Outline
SM5844AF is a special LSI for sampling rate converter, having a function to asynchronously covert the sample rate of the digital
audio signal. The input/output interface correspond to the input data of 16/20-bit word length and the output data of 16/18/20-bit
word length. Moreover, it integrates the digital de-emphasis filter, digital attenuator and other functions.
The package is a 44-pin QFP type, and the LSI is excellent in the cost performance.

32.0 kHz

H

H

44.1 kHz

X

L

48.0 kHz

L

H

L

L

16 Bit

Backward packing

L

H

MSB first

H

L

20 Bit

Forward packing

H

H

LSB first

Backward packing

16 Bit

H

H

18 Bit

Backward packing

H

L

20 Bit

L

H

Forward packing

L

L

16 Bit

H

H

18 Bit

IIS Mode

H

L

20 Bit

Forward packing

L

H

L

L

– 54 –

34, 35

SLAVE

Input with pull-up resistor

Mode setting of BCKO, LRCO terminal. H: Output terminal is selected. (Slave mode)
L: Input terminal is selected. (Master mode)

36*,37* THRUN

Input with pull-up resistor

Through mode setting of DOUT

H: Normal mode, L: Through mode

38

OCKSL

Input with pull-up resistor

System clock on the output side (OCLK) selection. H: 384fs, L: 256fs

39

OCLK

Input

Output system clock input

40

LRCO

Input/Output

Word clock output/input on the output side (fso)
Output/input mode is set from the slave terminal.

41, 42

BCKO

Input/Output

Bit clock output/input on the output side
Output/input mode is set from the slave terminal.

43, 44

DOUT

Output

Data output

In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.

Note 1:  "fsi" means the word clock (LRCI) on the input side, and "fso" means the work clock (LRCO) on the output side.
Note 2:  When H level is set, "open" is also applicable.
Note 3:  When the terminal of plural terminal Nos. for the same terminal name is used, it does not matter whether either or both

terminals are connected.

MCOM

MDT/FSI1

MCK/FSI2

MLEN/DEEM

ICLK

ICKSL

LRCI

RSTN

TST1N

TST2N

OW18N

OW20N

IISN

SLAVE

OCLK

OCKSL

THRUN

DMUTE

LRCO

BCKO

DOUT

STATE

IFM1

IFM2

BCKI

DI

MODE

De-emphasis

Attenuator Setting

Division on 

the Input Side

Input Timing 

Controller

Filter Characteristics

Selection 

Output Practice 

Timing Controller

Output Format

Controller

Clock Selection on the 

Output Side

Dither

Division on the 

Output Side

Mute

Generation

Direct Mute

Through Mode Switch

LRCI

BCKI

DI

Output Data 

Interface

Output Operation

Interpolation

Filter Operation

Attenuator

Operation Section

De-emphasis 

Operation

Input Data 

Interface

16

17

18

19

20

6

7

5

30

31

28

29

22

21

24

23

25

26

34

35

39

38

36

37

14

15

40

41 42

43 44

27

2

1

4

3

11 10

8

9

– 55 –

• Outline
The TDA1307 is an advanced oversampling digital filter employing bitstream conversion technology, which has been designed
for use in premium performance digital audio applications. Audio data is input to the TDA1307 through its multiple-format interface.
Any of the four formats (IIS, Sony 16, 18 or 20-bit) are acceptable. By using a highly accurate audio data processing structure,
including 8 times oversampling digital filtering and up to 4th order noise shaping, a high quality bitstream is produced which, when
used in the recommended combination with the TDA1547 bitstream DAC, provides the optimum in dynamic range and signal-to-
noise performance. With the TDA1307, a high degree of versatility is achieved by a multitude of functional features and their easy
accessibility; error concealment functions, audio peak data information and an advanced patented digital fade function are
accessible through a simple microprocessor command interface, which also provides access to various integrated system settings
and functions.

1

WS

Input

Word select input to data interface

2

SCK

Input

Clock input to data interface

3

SD

Input

Data input to interface

4

EFAB

Input (Note 1)

Error flag: (active HIGH) input from decoder chip indicating unreliable data

5

SBCL

Input

Subcode clock: a 10-bit burst clock (typ. 2.8224 MHz) input which synchronizes the subcode data

6

SBDA

Input

Subcode data: a 10-bit burst of data, including flags and sync bits, serially input once per
frame, clocked by burst clock input SBCL

7*

CDEC

Output

Decoder clock output: frequency division programmable by means of pins 14 (CLC1) and 17
(CLC2) to output 192, 256, 384 or768 times fs

8

V

DD3

—

Positive supply 3

9

Vss

2

—

Ground 2

10*

DOBM

Output

Digital audio output: this output contains digital audio samples which have received
interpolation, attenuation and muting plus subcode data. Transmission is in biphase-mark
code.

11*

DSL

Output

Digital silence detected (active LOW) on left channel

12*

DSR

Output

Digital silence detected (active LOW) on right channel

13

DSTB

Input (Note 2)

DOBM standby mode enforce pin (active HIGH)

14

CLC1

Input

Application mode programming pin for CDEC (pin 7) frequency division

15*

CMIC

Output

Clock output, provided to be used as running clock by microprocessor (in master mode only),
output 96fs

16

V

SS3

—

Ground 3

17

CLC2

Input

Application mode programming pin for CDEC (pin 7) frequency division

18

CDCC

Input

Master/Slave mode selection pin

19*

RESYNC

Output

Resynchronization: out-of-lock indication from data input section (active HIGH)

20

POR

Input (Note 2)

Power-on reset (active LOW)

21

V

DD1

—

Supply voltage 1

22

XTAL1

Input

Crystal oscillator terminal: local crystal oscillator sense

23

XTAL2

Output

Crystal oscillator output: drive output to crystal or forced input in slave mode

24

V

DDOSC

—

Positive supply connection to crystal oscillator circuitry

25

V

SSOSC

—

Ground connection to crystal oscillator circuitry

26*

MODE

Input (Note 2)

Evaluation mode programming pin (active LOW); in normal operation, this pin should be left
open-circuit or connected to the positive supply

27

DOL

Output

Data output left channel to bitstream DAC TDA1547

28*

NDOL

Output

Complementary data output left channel to TDA1547

29

V

DDAL

—

Positive supply connection to output data driving circuitry, left channel

30

V

SSAL

—

Ground connection to output data driving circuitry, left channel

31

V

SSAR

—

Ground connection to output data driving circuitry, right channel

32

V

DDAR

—

Positive supply connection to output data driving circuitry, right channel

33

DOR

Output

Data output right channel to TDA1547

34*

NDOR

Output

Complementary data output right channel to TDA1547

35

CDAC

Output

Clock output to bistream DAC TDA1547

36, 37

TEST1, TEST2

Input (Note 1)

Test mode input. In normal operation this pin should be connected to ground

38

DA

Input/Output

Bidirectional data line intended for control data from the microprocessor and peak data from

(Note 2)

the TDA1307

In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.

– 56 –

39

CL

Input (Note 2)

Clock input, to be generated by the microprocessor

40

Vss

1

—

Ground 1

41

V

DD2

—

Supply voltage 2

42

RAB

Input (Note 2)

Command/peak data request line

1fs AUDIO DATA INPUTS

WS

SCK

SD

EFAB

1

2

3

4

TDA1307

MULTIPLE FORMAT

INPUT INTERFACE

ERROR CONCELMENT,

INTERPOLATION, MUTING

DIGITAL

OUTPUT

DIGITAL SILENCE DETECTION

DEEMPHASIS FILTER

FIR HALFBAND FILTER

STAGE  1: 1fs to 2fs

DC-CANCELING FILTER

PEAK DETECTION

FADE FUNCTION

VOLUME CONTROL

FIR HALFBAND FILTER

STAGE 2: 2 fs to 4 fs

FIR HALFBAND FILTER

STAGE 3: 4 fs to 8 fs

DITHER AND SCALING

3rd/4th ORDER

NOISE SHAPER

27

28

35

34

33

26

DOL

NDOL CDAC NDOR DOR

MODE

BITSTREAM DATA OUTPUTS

MICROPROCESSOR INTERFACE

DA  38

CL  39

RAB  42

POR  20

VDD3  8

VDD1  21

VDDOSC  24

VDDAL  29

VDDAR  32

VDD2  41

DSR  12

DSL  11

TEST1  36

TEST2  37

19  RESYNC

10  DOBM
13  DSTB

5  SBCL
6  SBDA

CRYSTAL

OSCIL-
LATOR

25  VSSOSC

22  XTAL1

23  XTAL2

15  CMIC

7  CDEC

14  CLC1

17  CLC2

18  CDCC

9  VSS2

16  VSS3

30  VSSAL

31  VSSAR

40  VSS1

CLOCK GENERATION & DISTRIBUTION

WS

SCK

SD

EFAB

SBCL

SBDA

CDEC

VDDC3

VSSC2

DOBM

DSL

DSR

DSTB

CLC1

CMIC

VSSC3

CLC2

CDCC

RESYNC

POR

VDDC1

RAB

VDDC2

VSSC1

CL

DA

TEST2

TEST1

CDAC

NDOR

DOR

VDDAR

VSSAR

VSSAL

VDDAL

NDOL

DOL

MODE

VSSOSC

VDDOSC

XTAL2

XTAL1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

TDA1307

Notes
1. These pins are configured as internal pull-down.
2. These pins are configured as internal pull-up.