Sharp SM-SX100 (serv.man2) Service Manual ▷ View online
SM-SX100
– 49 –
No
Yes
Is any 1-bit signal from Pins 27 and 33 of IC807 output
to RLY801?
to RLY801?
Check IC808, IC809, IC811, IC812 and IC813.
No
Yes
Does RLY801 and RLY802 operate?
Check the operation of Q801 and Q802 and the wiring of
each to the microcomputer IC904.
each to the microcomputer IC904.
Check the wiring from B1108/CNS108 to CNP107 and
1-bit amplifying unit.
1-bit amplifying unit.
From the front page
No
• It does not sound at DIGITAL1 or DIGITAL4 alone.
Yes
Is any digital signal output from Pin 8 or 10 of IC802?
Check RX801, RX802 and IC802.
No
Is any digital signal output from Pin 9 of IC801?
Check IC801 and input A, B terminal logic.
No
• It does not sound at DIGITAL2 or DIGITAL3 alone.
Yes
Is any digital signal output from Pin 8 or 6 of IC803?
Check CNS803.
Check the wiring from CNS803 to IC803.
Check the wiring from CNS803 to IC803.
No
Is any digital signal output to Pin 9 of IC801?
Check IC801 and input A, B terminal logic.
No
• 1-bit amplifying section check (Signal is output from CNP107 and CNP108 but it does not sound.)
Yes
Is any signal output form Pins 2, 3, 5 and 6 of ICA1?
(Fig. 50-1)
(Fig. 50-1)
Check the waveform of the input pin, ICA1, voltage supplied
to ICA1 and ICA1 oscillating circuit.
to ICA1 and ICA1 oscillating circuit.
No
Are the waveforms of QA1 to QA8 proper?
(Fig. 50-2, Fig. 50-3, Fig. 50-4)
(Fig. 50-2, Fig. 50-3, Fig. 50-4)
Check ICA2, ICA3, QA1 to QA7.
Yes
No
Are the waveforms of ICA4 to ICA7 proper? (Fig. 50-5)
Check ICA4 to ICA7.
Yes
No
Are the waveforms of QA9 to QA16 proper?
(Fig. 50-6, Fig. 50-7)
(Fig. 50-6, Fig. 50-7)
Check RA53 to FA60 and QA9 to QA16.
Yes
No
Is any signal output from CNWAM6 and CNWAM7?
Check LA802 to LA808.
Check the soldering.
Check the soldering.
Yes
Check the surrounding of the relay PWB.
SM-SX100
– 50 –
No
• 1-bit amplifying section check (power trouble/protector activation)
Yes
Don't the protector activate together with drop of voltage
±
32V if CNWAM4 and CNWAM3 are disconnected?
Recheck the main body section.
No
Does the oscillating circuit operate? Check Pin 9.
Replace ICA1.
Check CXA1 crystal and CA8, CA9.
Check CXA1 crystal and CA8, CA9.
Yes
Check ICA4 to ICA7, CA36 to CA39, QA9 to QA16 and
RA53 to RA60.
RA53 to RA60.
Figure 50-1
1
• OUTR(+), OUTR(-)
• OUTL(+), OUTL(-)
• OUTL(+), OUTL(-)
Observe
each pair.
each pair.
OUTR(+),
(OUTL(+))
(OUTL(+))
OUTR(-),
(OUTL(-))
(OUTL(-))
3
Observe
each pair.
each pair.
• QA1, QA5
• QA2, QA6
• QA3, QA7
• QA4, QA8
• QA2, QA6
• QA3, QA7
• QA4, QA8
QA2
(QA1, 3, 4)
BASE
QA6
(QA5, 7, 8)
BASE
4
Observe
each pair.
each pair.
• QA1, QA5
• QA2, QA6
• QA3, QA7
• QA4, QA8
• QA2, QA6
• QA3, QA7
• QA4, QA8
QA2
(QA1, 3, 4)
EMITER
QA6
(QA5, 7, 8)
EMITER
5
Observe
each pair.
each pair.
• QA1, QA5
• QA2, QA6
• QA3, QA7
• QA4, QA8
• QA2, QA6
• QA3, QA7
• QA4, QA8
QA1
(QA2, 3, 4)
COLECTOR
QA5
(QA6, 7, 8)
COLECTOR
6
Observe Li and Hi of
ICA4 to 7 of each.
ICA4 to 7 of each.
Li
Hi
7
Observe
each pair.
each pair.
• QA9, QA11
• QA10, QA12
• QA13, QA15
• QA14, QA16
• QA10, QA12
• QA13, QA15
• QA14, QA16
QA10
(QA9,13,14)
GATE
QA12
(QA11,15,16)
GATE
8
Observe SW section
of Lch and Rch of each.
of Lch and Rch of each.
Figure 50-2
Figure 50-3
Figure 50-4
Figure 50-5
Figure 50-6
Figure 50-7
SM-SX100
– 51 –
IC804 VHiYM3436D/-1: Digital Interface Receiver (YM3436D)
1
DAUX
Input
Audio data auxiliary input
2*
HDLT
Output
Asynchronous buffer operation flag output
3
DOUT
Output
Audio data output
4*
VFL
Output
Validity flag output
5*
OPT
Output
Synchronous signal output (fs) for DAC
6*
SYNC
Output
Synchronous signal output (fs) for DSP
7
MCC
Output
Bit clock output (64fs)
8
WC
Output
Word clock output (fs)
9*
MCB
Output
Bit clock output (128fs)
10
MCA
Output
Bit clock output (256fs)
11
SKSY
Input
Clock synchronizing control input
12
XI
Input
Quartz oscillator connection, or external clock input (256fs)
13
XO
Output
Quartz oscillator connection
14*
P256
Output
VCO clock output (When clocked, 256fs)
15
LOCKN
Output
PLL lock flag output ('L': Clocked, 'H': Unlocked)
16
VSS
—
Grand (logic system)
17*
TST2
Output
LSI test terminal (As usual, don't connect it.)
18
DIM1
Input
Data input mode selection 1
19
DIM0
Input
Data input mode selection 0
20
DOM1
Input
Data output mode selection 1
21
DOM0
Input
Data output mode selection 0
22
KM1
Input
Clock mode selection 1 ('H': PLL auto switch, 'L': XI fixed)
23
RSTN
Input
System reset input (active low)
24
VDDA
—
+5V power supply (VCO system. Externally connect it to VDD.)
25
CTLN
Input
VCO control input
26
PCO
Output
PLL phase comparative output
27*
N.C.
—
Not used
28
CTLP
Input
VCO adjustment input (As usual, connect it to VSSA.)
29
VSSA
—
Grand (VCO system. Externally connect it to VSS.)
30*
TSTN
Input
LSI test terminal (As usual, it is not connected.)
31
KM2
Input
Clock mode selection 2 ('H": PLL synchronization, 'L': XI synchronization)
32
KM0
Input
Clock mode selection 0 ('H': EXTW input, 'L': DDIN input)
33
FS1
Output
Sampling frequency code output 1/channel status output
34
FS0
Output
Sampling frequency code output 0/user data output
35
CSM
Input
Channel status, user data output method selection
36
EXTW
Input
External synchronizing auxiliary input, Word clock
37
DDIN
Input
EIAJ(AES/EBU) digital audio interface signal input
38*
LR
Output
PLL word clock output (When locked, fs)
39
VDD
—
+5V power (logic system)
40
ERR
Output
Data error flag output
41
EMP
Output
Emphasis control code output/block start synchronizing signal output
42*
CDO
Output
Microcomputer interface data output
43
CCK
Input
Microcomputer interface clock input
44
CLD
Input
Microcomputer interface load input
Pin No.
Port Name
Input/Output
FUNCTION TABLE OF IC
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
• Outline
YM3436D(DIR2) is a LSI which receives and demodulate the digital/audio/interface/format signals which comply with EIAJ CP-
340 and AES/EBU. Keeping the features of the existing YM3623B(DIR), it is designed to not only strengthen the external
synchronization, error process and other functions but also be more general for the channel status, user data output and other
general applications.
YM3436D(DIR2) is a LSI which receives and demodulate the digital/audio/interface/format signals which comply with EIAJ CP-
340 and AES/EBU. Keeping the features of the existing YM3623B(DIR), it is designed to not only strengthen the external
synchronization, error process and other functions but also be more general for the channel status, user data output and other
general applications.
Function
SM-SX100
– 52 –
Figure 52 BLOCK DIAGRAM OF IC
SEL
PLL
EIAJ(AES/EBU)
Digital Audio
Interface Decoder
Microcomputer Interface
Data Clock
Control
S/P
P/S
Asynchronous
Buffer
(1 word per
each of
L and R)
System Clock
Timing Generator
EXTW
DDIN
CSM
ERR
EMP
EMP
FS1,0
CCK,CLD
CDO
DAUX
DIM1,0
HDLT
DOM1,0
DOUT
VFL
TST2
TSTN
RSTN
MCA,MCB,MCC,
WC,SYNC,OPT
KM0
VDDA
VSSA
PCO
CTLP,CTLN
LR
LOCKN
P256
KM2
XI
XO
KM1
SKSY
VDD
VSS
36
37
35
40
41
41
43 44
42
1
18 19
2
20 21
3
4
17
30
23
5
10
~
16
39
11
22
13
12
31
14
15
38
25 28
26
29
24
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
33
32
31
30
29
28
27
26
25
24
23
44
43
42
41
40
39
38
37
36
35
34
DAUX
HDLT
DOUT
VFL
OPT
SYNC
MCC
WC
MCB
MCA
SKSY
XI
XO
P256
LOCKN
VSS
TST2
DIM1
DIM0
DOM1
DOM0
KM1
FS1
KM0
KM2
TSTN
VSSA
CTLP
(NC)
PCO
CTLN
VDDA
RSTN
CLD
CCK
CDO
EMP
ERR
VDD
LR
DDIN
EXTW
CSM
FS0
IC804 VHiYM3436D/-1: Digital Interface Receiver (YM3436D)
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