Sharp CD-DVD500 (serv.man18) Service Manual ▷ View online
– 75 –
CD-DVD500H
53
P1CI
Input
C input. (DVD)
54
P1BI
Input
B input. (DVD)
55
P1AI
Input
A input. (DVD)
56
GNDR
—
GND terminal. (RF)
57
LDP2
Input
APC polarity 2.
58
P2AI
Input
A input. (CD)
59
P2BI
Input
B input. (CD)
60
P2CI
Input
C input. (CD)
61
P2DI
Input
D input. (CD)
62
GNDS
—
GND terminal. (Servo)
63
P2FP
Input
FE+ input. (CD)
64
P2Fn
Input
FE– input. (CD)
IC3301 VHiTA1323F+-1: RF Signal Processor (TA1323F) (2/2)
Terminal Name
Pin No.
Input/Output
Function
Figure 75 BLOCK DIAGRAM OF IC
P1TP
P1TN
LDO1
MDI1
EQF
EQB
VrA
RFDC
TCC1
GND2
NC
NC
Vcc2
DPDB
FEB
TEB
RFS
VccR
RFOp
RFOn
RPP
RPB
RPO
RPZ
NC
VccS
DFTN
FEO
TEO
LVL
VccP
VCKF
P1FN
P1FP
LDP1
P1DI
P1CI
P1BI
P1AI
GNDR
LDP2
P2AI
P2BI
P2CI
P2DI
GNDS
P2FP
P2FN
GND
P2TP
P2TN
LDO2
MDI2
V
rD
V
rfil
V
dd
DPAC
DPBD
DPD1
DPD2
SCB
SCL
SCD
V
RCK
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Time
constant
adjustment
RF Ripple
creation
Output
Amp
T-gain
Adjust
Adjust
sel-PD
sel-PD
sel-PD
Level
detect
F-gain
Adjust
Adjust
mode-IC
R-gain
Adjust
3Beam-TE
creation
DPD-TE
creation
FE creation
EQ
APC1
APC2
Vref
BUS
sel-RF
sel-FE
sel-TE
sel-DPD
sel-LVL
mode-TE
F-gain
Adjust
Adjust
DPDB
TEB
FEB
TEB
TCC1
VrA
tcc1 (BUS)
TE-gain
Adjust
FE-gain
Adjust
DC
FB
CD-DVD500H
– 76 –
1
VDD1
Input
Digital power supply +3.3 V.
2
HADR0
Input
CPU Address bus.
3
HADR1
Input
CPU Address bus.
4
HADR2
Input
CPU Address bus.
5
HADR3
Input
CPU Address bus.
6
HADR4
Input
CPU Address bus.
7
HADR5
Input
CPU Address bus.
8
HADR6
Input
CPU Address bus.
9
HADR7
Input
CPU Address bus.
10
VSS
—
Digital GND.
11
VDD1
Input
Digital power supply +3.3 V.
12
HDAT0
Input/Output
CPU Data bus.
13
HDAT1
Input/Output
CPU Data bus.
14
HDAT2
Input/Output
CPU Data bus.
15
HDAT3
Input/Output
CPU Data bus.
16
HDAT4
Input/Output
CPU Data bus.
17
HDAT5
Input/Output
CPU Data bus.
18
HDAT6
Input/Output
CPU Data bus.
19
HDAT7
Input/Output
CPU Data bus.
20
HRD
Input
CPU Read signal.
21
HWR
Input
CPU write signal.
22
HAS
Input
CPU address strobe.
23
HCS1
Input
CPU chip select signal 1. (Track Buffer Operation)
24
HCS2
Input
CPU chip select signal 2. (bus Voltage Transfer)
25
VSS
—
Digital GND.
26
VDD1
Input
Digital power supply +3.3 V.
27
HWAIT
Output
CPU wait signal. (Open drain)
28
HINT
Output
CPU interrupt signal. (Open drain)
29
VSS
—
Digital GND.
30-38
PDO[0]-[8]
Output
Output DVD/CDdata.
39
VSS
—
Digital GND.
40
VDD1
Input
Digital power supply +3.3 V.
41
PSYCO
Output
Output data selector sync signal.
42
PDRQO
Output
Output data transfer block signal.
43
PDCKO
Output
Output data transfer clock.
44
VSS
—
Digital GND.
45
VDD2
Input
Digital power supply +5 V.
46
DVDREQ
Input
Request signal input.
47
PDCKI
Input
Input data transfer clock.
48
PDRQI
Input
Input data transfer block signal.
49
PSYCI
Input
Input data selector sync signal.
50
VSS
—
Digital GND.
51
VDD2
Input
Digital power supply +5 V.
52-60
PDI[8]-[0]
Output
Input DVD/CD data.
61
VSS
—
Digital GND
62
VDD1
Input
Digital power supply +3.3 V.
63
VSS
—
Digital GND.
64
VDD2
Input
Digital power supply +5 V.
65-72
5VBUS[7]-[0]
Input/Output
CPU bus 5 V conversion input/output.
73*,74*
N.C.
—
—
75
VSS
—
Digital GND.
IC3508 RH-iX1761GEZZ: Track Buffer Interface (IX1761GE) (1/2)
Terminal Name
Pin No.
Input/Output
Function
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
– 77 –
CD-DVD500H
76
VDD1
Input
Digital power supply +3.3 V.
77
5VBUFO[B]
Output
5 V buffer output B.
78
5VBUFI[B]
Output
5 V buffer input B. (3.3 V input)
79
5VBUFO[A]
Output
5 V buffer output A.
80
5VBUFI[A]
Output
5 V buffer input A. (3.3 V input)
81*
GPO[3]
Output
General-purpose output terminal. (CPU control)
82*
GPO[2]
Output
General-purpose output terminal. (CPU control)
83*
GPO[1]
Output
General-purpose output terminal. (CPU control)
84*
GPO[0]
Output
General-purpose output terminal. (CPU control)
85
VSS
—
Digital GND.
86
VDD1
Input
Digital power supply +3.3 V.
87*
LI[1]
Input
Gate Input[1].
88*
LI[2]
Input
Gate Input[2].
89*
BUFO[C]
Output
Schmitt trigger buffer output C.
90*
BUFI[C]
Input
Schmitt trigger buffer input C.
91
BUFO[B]
Output
Schmitt trigger buffer output B.
92
BUFI[B]
Input
Schmitt trigger buffer input B.
93
BUFO[A]
Output
Schmitt trigger buffer output A.
94
BUFI[A]
Input
Schmitt trigger buffer input A.
95
TEST0
Input
Test terminal 0 (Normal: Low, Test: Hi) Function.
96
TEST1
Input
Test terminal 1 (Normal: Low, Test: Hi) RAM.
97
TEST2
Input
Test terminal 2 (Normal: Low, Test: Hi) Pin.
98*
N.C.
—
—
99
MRST
Input
27 MHz Input terminal.
100
VSS
—
Digital GND.
IC3508 RH-iX1761GEZZ: Track Buffer Interface (IX1761GE) (2/2)
Terminal Name
Pin No.
Input/Output
Function
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Figure 77 BLOCK DIAGRAM OF IC
VSS
PSYCI
PDRQI
PDCKI
DVDREQ
VDD2
VSS
PDCKO
PDRQO
PSYCO
VDD1
VSS
PDO[8]
PDO[7]
PDO[6]
PDO[5]
PDO[4]
PDO[3]
PDO[2]
PDO[1]
PDO[0]
VSS
HINT
HWAIT
VDD1
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
VDD1
HADR0
HADR1
HADR2
HADR3
HADR4
HADR5
HADR6
HADR7
VSS
VDD1
HDAT0
HDAT1
HDAT2
HDAT3
HDAT4
HDAT5
HDAT6
HDAT7
HRD
HWR
HAS
HCS1
HCS2
VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
VDD1
5VBUFO[B]
5VBUFI[B]
5VBUFO[A]
5VBUFI[A]
GPO[3]
GPO[2]
GPO[1]
GPO[0]
VSS
VDD1
LI[1]
LI[2]
BUFO[C]
BUFI[C]
BUFO[B]
BUFI[B]
BUFO[A]
BUFI[A]
TEST0
TEST1
TEST2
NC
MRST
VSS
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
VSS
NC
NC
5VBUS[0]
5VBUS[1]
5VBUS[2]
5VBUS[3]
5VBUS[4]
5VBUS[5]
5VBUS[6]
5VBUS[7]
VDD2
VSS
VDD1
VSS
PDI[0]
PDI[1]
PDI[2]
PDI[3]
PDI[4]
PDI[5]
PDI[6]
PDI[7]
PDI[8]
VDD2
IPD
Interface
Host
Interface
RAM
(4.2 Kbyte)
Memory
CTL
Error
Detect
ID
Detect
GPO
Interface
OPD
Interface
Timing
Gen.
ZZ
ZZ
ZZ
CD-DVD500H
– 78 –
1*
LD-FWD
Loading driver FWD input terminal.
2
SL_IN(+)
CH 1 Former stage amplifier nonreverse input terminal.
3
SL_IN(-)
CH 1 Former stage amplifier reverse input terminal.
4
SLOUT
CH 1 Former stage amplifier output terminal.
5
SP_IN(+)
CH 2 Former stage amplifier nonreverse input terminal.
6
SP_IN(-)
CH 2 Former stage amplifier reverse input terminal.
7
SP_OUT
CH 2 Former stage amplifier output terminal.
8
VCC
Power terminal.
9*
LD(-)
Loading driver Negative output.
10*
LD(+)
Loading driver Positive output.
11
SPIN(-)
Driver CH 2 Negative output .
12
SPIN(+)
Driver CH 2 Positive output.
13
SL(-)
Driver CH 1 Negative output.
14
SL(+)
Driver CH 1 Positive output.
15
V04(+)
Driver CH 4 Negative output.
16
V04(-)
Driver CH 4 Positive output.
17
V03(+)
Driver CH 3 Negative output.
18
V03(-)
Driver CH 3 Positive output.
19
GND
Ground terminal.
20
BIAS
Bias input terminal.
21
MUTE
Mute control terminal.
22
FO_OUT
CH 3 Former stage amplifier output terminal.
23
FO_IN(-)
CH 3 Former stage amplifier reverse input terminal.
24
FO_IN(+)
CH 3 Former stage amplifier nonreverse input terminal .
25
TR_OUT
CH 4 Former stage amplifier output terminal.
25
TR_OUT
CH 4 Former stage amplifier output terminal.
26
TR_IN(-)
CH 4 Former stage amplifier reverse input terminal.
27
TR_IN(+)
CH 4 Former stage amplifier nonreverse input terminal.
28*
REV
Loading driver REV input terminal.
IC3801 VHiBA5984FP-1: Motor Driver (BA5984FP)
Terminal Name
Pin No.
Function
Positive and negative output the driver have polarity with respect to input.
(An example: 4 pin terminal voltage ‘HIGH’: 14 pin terminal voltage ‘HIGH’)
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
(An example: 4 pin terminal voltage ‘HIGH’: 14 pin terminal voltage ‘HIGH’)
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Figure 78 BLOCK DIAGRAM OF IC
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
-
+
-
+
-
+
10K
-
+
10K
16K
16K
-
+
-
+
-
+
10K
16K
-
+
10K
16K
MUTE
REV OUTF
FWD OUTR
FWD OUTR
Loading Driver
VCC
-
+
10K
10K
10K
10K
-
+
10K
-
+
10K
-
+
10K
10K
- +
Level
Shift
- +
Level
Shift
-
+
10K
10K
10K
10K
-
+
10K
-
+
10K
-
+
10K
10K
- +
Level
Shift
- +
Level
Shift
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