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– 66 –

52

AVref0

—

Analog reference potential 0

53

P10/ANI0

Input

Key input 0 (AD port)

54

P11/ANI1

Input

Key input 1 (AD port)

55

P12/ANI2

Input

Key input 2 (AD port)

56

P13/ANI3

Input

Key input 3 (AD port)

57

P14/ANI4

Input

Key input 4 (AD port)

58

P15/ANI5

Input

Level meter input L-ch

59

P16/ANI6

Input

Tuner state input

60

P17/ANI7

Input

Level meter input R-ch

61

Avss

—

Analog GND

62

P130/ANO0

Input

Tape mecha select single/reverse

63

P131/ANO1

Output

Not used

64

AVref1

Input

Analog reference potential 1

65

P70/RxD2/SI2

Input

Not used

66

P71/TxD2/SO2

Output

Not used

67

P72/ASCK2/SCK2

Input

Not used

68

P20/RxD1/SI1

Input

Tuner data input

69

P21/TxD1/SO1

Output

Tuner data output

70

P22/ASCK1/SC

Output

Tuner clock output

71

P23/PCL

Output

Not used

72

P24/BUZ

Output

Not used

73

P25/SI0/SDA0

Input/Output

Control output read/write to LCD driver

74

P26/SO0

Output

Not used

75

P27/SCK0/SCL0

Output

Control output clock to LCD driver

76

P80/A0

Input

CAM A switch e

77

P81/A1

Input

CAM A switch d

78

P82/A2

Input

CAM A switch c

79

P83/A3

Input

CAM A switch b

80

P84/A4

Input

CAM A switch a

81

P85/A5

Input

TRAY identification switch a

82

P86/A6

Input

TRAY identification switch b

83

P87/A7

Input

TRAY identification switch c

84

P40/AD0

Input

CAM C switch b

85

P41/AD1

Input

CAM C switch a

86

P42/AD2

Output

CD LSI chip enable

87

P43/AD3

Output

CD LSI clock

88

P44/AD4

Input/Output

CD LSI data input/output

89

P45/AD5

Input/Output

CD LSI data input/output

90

P46/AD6

Input/Output

CD LSI data input/output

91

P47/AD7

Input/Output

CD LSI data input/output

92

P50/A8

Output

CD LSI reset

93

P51/A9

Output

CD LSI RW switching

94

P52/A10

Input

CD pickup inner switch input

95

P53/A11

Output

Tray motor forward rotation

96

P54/A12

Output

Tray motor reverse rotation

97

P55/A13

Output

CAM motor forward rotation

98

P56/A14

Output

CAM motor reverse rotation

99

P57/A15

Output

TAPE REC mute

100

Vss

Input

Ground potertial connected to VSS

– 67 –

1

VSS

Input

GND

2

DATA

Input

Serial data input

3

CLOCK

Input

Serial clock input

4

LCK

Input

Latch clock input

5

Q0

Output

Panel LED

6

Q1

Ourput

> I I LED

7

Q2

Output

<< LED

8

Q3

Output

>> LED

9

Q4

Output

Stop LED

10

Q5

Output

Not used

11

Q6

Output

CD 6 LED

12

Q7

Output

CD 5 LED

13

Q8

Output

CD 4 LED

14

Q9

Output

CD 3 LED

15

Q10

Output

CD 2 LED

16

Q11

Output

CD 1 LED

17

OE

Output

Output enable

18

VDD

Input

Power supply

In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.

1

VSS

Input

GND

2

DATA

Input

Serial data input

3

CLK

Input

Serial clock input

4

LCK

Input

Latch clock input

5

Q0

Output

For CD power control

6*

Q1

Output

Not used

7*

Q2

Output

Not used

8*

Q3

Output

Not used

9

Q4

Output

Not used

10*

Q5

Output

Not used

11*

Q6

Output

Panel control switch

12

Q7

Output

Panel control output close

13

Q8

Output

Panel control output open

14

Q9

Output

Fan motor ON/OFF

15

Q10

Output

Not used

16

Q11

Output

Not used

17

OE

Output

Output enable

18

VDD

Input

Power supply

– 68 –

In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
(*): Normaly the output pin. Used as an I/O pin in test mode, which is not available to user applications.

1

VREF

Output

Reference voltage output (Vdda/2)

2

MPXIN

Input

Baseband (multiplexed) signal input

3

Vdda

—

Analog power supply (+5V)

4

Vssa

—

Analog ground

5

FLOUT

Output

Subcarrier output (fulter output)

6

CIN

Input

Subcarrier input (comparator input)

7

T1

Input

Test input (This pin must always be connected to ground.)

8

T2

Input

Test input (standby control)
0: Normal operation

1: standby state (crystal oscillator stopped)

9*

T3 (RDCL)

Input/Output (*)

Test I/O (RDS clock output)

10*

T4 (RDDA)

Input/Output (*)

Test I/O (RDS data output)

11*

T5 (RSFT)

Input/Output (*)

Test I/O (soft-decision control data output)

12

XOUT

Output

Crystal oscillator output (4.332/8.664 MHz)

13

XIN

Input

Crystal oscillator input (external reference signal input)

14

Vddd

—

Digital power supply (+5V)

15

Vssd

—

Digital ground

16*

T6

Input/Output (*)

Test I/O (error status, regenerated carrier, TP, error block count outputs)

(ERROR/57K/TP/BE1)

17*

T7

Input/Output (*)

Test I/O (error correction status, SK detection, TA, error block count outputs)

(CORREC/ARI-ID/TA/BE0)

18*

SYNC

Input/Output (*)

Block synchronization detection output

19*

RDS-ID

Output

RDS detection output

20

DO

Output

Data output

21

CL

Input

Clock input

22

DI

Input

Data input

    Serial data interface (CCB)

23

CE

Input

Chip enable

24

SYR

Input

Synchronization and RAM address reset (active high)

VREF

FLOUT

CIN

Vddd

Vssd

RDS-ID

SYNC

SYR

XOUT

XIN

DO

CL

DI

CE

T1

T2

T3 to T7

MPXIN

Vssa

Vdda

REFERENCE

VOLTAGE

ANTIALIASING

FILTER

57kHz

BPF

(SCF)

VREF

SMOOTHING

FILTER

+

_

PLL

(57kHz)

CLOCK

RECOVERY

(1187.5Hz)

DATA

DECODER

SYNC/EC CONTROLLER

SYNC

DETECT-2

SYNC

DETECT-1

ERROR CORRECTION

(SOFT DECISION)

CLK(4.332MHz)

OSC/DIVIDER

RAM

(24 BLOCK DATA)

MEMORY CONTROL

CCB

TEST

3

1

5

6

4

2

20

21
22

23

13

12

24

18

19

15

14

7

8

9~11,

16,17

– 68 –

In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
(*): Normaly the output pin. Used as an I/O pin in test mode, which is not available to user applications.

1

VREF

Output

Reference voltage output (Vdda/2)

2

MPXIN

Input

Baseband (multiplexed) signal input

3

Vdda

—

Analog power supply (+5V)

4

Vssa

—

Analog ground

5

FLOUT

Output

Subcarrier output (fulter output)

6

CIN

Input

Subcarrier input (comparator input)

7

T1

Input

Test input (This pin must always be connected to ground.)

8

T2

Input

Test input (standby control)
0: Normal operation

1: standby state (crystal oscillator stopped)

9*

T3 (RDCL)

Input/Output (*)

Test I/O (RDS clock output)

10*

T4 (RDDA)

Input/Output (*)

Test I/O (RDS data output)

11*

T5 (RSFT)

Input/Output (*)

Test I/O (soft-decision control data output)

12

XOUT

Output

Crystal oscillator output (4.332/8.664 MHz)

13

XIN

Input

Crystal oscillator input (external reference signal input)

14

Vddd

—

Digital power supply (+5V)

15

Vssd

—

Digital ground

16*

T6

Input/Output (*)

Test I/O (error status, regenerated carrier, TP, error block count outputs)

(ERROR/57K/TP/BE1)

17*

T7

Input/Output (*)

Test I/O (error correction status, SK detection, TA, error block count outputs)

(CORREC/ARI-ID/TA/BE0)

18*

SYNC

Input/Output (*)

Block synchronization detection output

19*

RDS-ID

Output

RDS detection output

20

DO

Output

Data output

21

CL

Input

Clock input

22

DI

Input

Data input

    Serial data interface (CCB)

23

CE

Input

Chip enable

24

SYR

Input

Synchronization and RAM address reset (active high)

VREF

FLOUT

CIN

Vddd

Vssd

RDS-ID

SYNC

SYR

XOUT

XIN

DO

CL

DI

CE

T1

T2

T3 to T7

MPXIN

Vssa

Vdda

REFERENCE

VOLTAGE

ANTIALIASING

FILTER

57kHz

BPF

(SCF)

VREF

SMOOTHING

FILTER

+

_

PLL

(57kHz)

CLOCK

RECOVERY

(1187.5Hz)

DATA

DECODER

SYNC/EC CONTROLLER

SYNC

DETECT-2

SYNC

DETECT-1

ERROR CORRECTION

(SOFT DECISION)

CLK(4.332MHz)

OSC/DIVIDER

RAM

(24 BLOCK DATA)

MEMORY CONTROL

CCB

TEST

3

1

5

6

4

2

20

21
22

23

13

12

24

18

19

15

14

7

8

9~11,

16,17