Sharp AN-PR1100H Service Manual ▷ View online
AN-PR1100H
7 – 11
ICM10 VHiLC750512-1: Audio Enhancer (LC750512) (2/2)
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Pin No.
Terminal Name
Input/Output
Function
62
XPDESC
Input
DSP power down release signal (L-Active).
63*
PDEN
Output
DSP power down signal (H-Active).
64
DVSS2
—
Digital GND.
65
DVDD2
Input
Digital power supply (+1.8V).
66
PWDB
Input
Power down input (L-Active).
67
RSTB
Input
Reset input (L-Active).
68
INTB
Input
Interrupt input (“H” Fixed input).
69
MCUIFSEL
Input
Microprocessor I/F (CCB: Low; I2C: High). Select input.
70
CE
Input
Microprocessor I/F chip enable.
71
SCL/CL
Input
Microprocessor I/F clock input.
72
I2CBUSY/DI
Input/Output
Microprocessor I/F data input/12CBUSY output (H-Active).
73
SDA/DO
Input/Output
Microprocessor I/F data input/output (Nch open drain).
74
DVSS3
—
Digital GND.
75
DVDD3
Input
Digital power supply (+1.8V).
76
MRREQ
Output
DSP-MCU communication error flag (H-Active).
77*
GPFLAG
Output
DSP-MCU general-purpose flag (H-Active).
78*
EMPF
Output
CCB input register status monitor flag.
79
CVSS3
—
Digital GND.
80
CVDD3
Input
Digital power supply (+3.3 V).
PLL
VCO
VCO
Program ROM
Data RAM
DSP CORE
24bit
CCB or I C
XIN
13
12
XOUT
SCL/CL
I2CBUSY/DI
SDA/DO
DAC
(20bit)
L.P.F.
R
Vref
EVRINL
AOUT1
DAOUTL
DAC
(20bit)
L.P.F.
R
Vref
DAOUTR
EVRINR
AOUT2
LRCKO
BCKO
DATAO0
DATAO0
DATAO1
CE
ADC
(20bit)
ADC
(20bit)
BCKI
DATAI
PLLPWPR
XSEL0,1,2
MCUIFSEL
RSTB
PWDB
PDEN
XPDESC
INTB
TEST7,5-0
TEST6
SCKI
SCKO
VREF2
Delay RAM
DVSS1-4
DVDD1-4
VREF1
Audio I/F
Audio I/F
CVSS1-4
CVDD1-4
BVSS1
BVDD1
AVSS1-4
AVDD1-4
PLLDVSS
PLLDVDD
PLLAVSS
PLLAVDD
EMPF
GPFLAG
MRREQ
XVSS
XVDD
PLLGNDR
LRCKI
INL
INR
DATAO2
Audio I/F
Audio I/F
38
37
47
48
49
1
2
42,43,44
78
77
76
70
71
72
73
69
67
66
63
62
68
41
50
53
7,817,18,19,20,41
35
36
11
14
9,51,64,74
10,52,65,75
16,45,79,60
15,46,61,80
23,26,33,39
24,25,34,40
5
4
3
55
56
57
58
59
32
31
30
27
28
29
6
21
22
2
Figure 7-5 BLOCK DIAGRAM OF IC
AN-PR1100H
7 – 12
[2] FL Display
FL100 VVKNA10SM54-1
P1
1G
2G
a
b
k
j
h
f
m
d
g
p
e
n
r
c
a
b
k
j
h
f
m
d
g
p
e
n
r
c
a
b
k
j
h
f
m
d
g
p
e
n
r
c
a
b
k
j
h
f
m
d
g
p
e
n
r
c
a
Col
Col
b
k
j
h
f
m
d
g
p
e
n
r
c
a
b
k
j
h
f
m
d
g
p
e
n
r
c
a
b
k
j
h
f
m
d
g
p
e
n
r
c
a
b
k
j
h
f
m
d
g
p
e
n
r
c
Dp
Dp
3G
4G
5G
6G
7G
8G
9G
10G
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
P16
(DIGITAL)
(PL II)
(VS)
ANODE CONNECTION
GRID ASSIGNMENT
1G
2G
3G
4G
5G
6G
7G
8G
9G
10G
a
b
k
j
h
f
g
e
r
p
d
(2G-9G)
n
c
m
Col
Dp
Col
Dp
AN-PR1100H
7 – 13
OUTER DIMENSIONS
PIN CONNECTION
AN-PR1100H
7 – 14
-MEMO-
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