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Model
AN-PR1100H
Pages
108
Size
14.32 MB
Type
PDF
Document
Service Manual
Brand
Device
Audio / Home Theatre
File
an-pr1100h.pdf
Date
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Sharp AN-PR1100H Service Manual ▷ View online

AN-PR1100H
7 – 3
ICM7 RH-IXA105AW00: System Microcomputer ( IXA105AW ) (3/3)
Figure 7-1 BLOCK DIAGRAM OF IC
POWER
AVCC
VREF
B_CHECK
GND
TUNER_SM
MP_SW
KEY1
KEY_POWER
SYS-PROTECT
AREA
NC
CCB_CE
CCB_DI
CCB_CL
CCB_DO
KEY_FUNCTIO
N
AVCK2
AVCK1
TIMER_LED
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
P
97/
A
D
T
R
G
/SIN
4
AVCC
VREF
P
100/
A
N
0
AVSS
P
101/
A
N
1
P
102/
A
N
2
P
103/
A
N
3
P
104/
A
N
4/
K
I0
P
105/
A
N
5/
K
I1
P
106/
A
N
6/
K
I2
P
107/
A
N
7/
K
I3
P
00/
D
0
P
01/
D
1
P
02/
D
2
P
03/
D
3
P
04/
D
4
P
05/
D
5
P
06/
D
6
P
07/
D
7
FUNC_DIG3
1
P96/ANEX1
/SOUT4
P10/D8 80
RDS DO
FUNC_DIG2
2
P95/ANEX0
/CLK4
P11/D9 79
RDS RST
FUNC_DIG1
3
P94/DA1
/TB4IN
P12/D10 78
RDS CLK
FUNC_ANA
4
P93/DA0
/TB3IN
P13/D11 77
RDS RDY
FAN_LOCK
5
P92/TB2IN
/SOUT3
P14/D12 76
NC
SYS_STOP
6
P91/TB1IN
/SIN3
P15/D13/INT3 75
RX-IN
NC
7
P90/TB0IN
/CLK3
P16/D14/INT4 74
NC
BYTE 
8
BYTE
P17/D15/INT5 73
NC
CNVSS
9
CNVSS
P20/A7(/D0/-) 72
NC
XCIN
10 P87/XCIN
P21/A7(/D1/D0) 71
NC
XCOUT
11 P86/XCOUT
P22/A7(/D2/D1) 70
NC
RESET
12 RESET
P23/A7(/D3/D2) 69
NC
X_OUT
13 XOUT
P24/A7(/D4/D3) 68
NC
GND
14 VSS
P25/A7(/D5/D4) 67
NC
X_IN
15 XIN
P26/A7(/D6/D5) 66
NC
VCC
16 VCC
P27/A7(/D7/D6) 65
NC
NMI
17 P85/NMI
VSS 64
GND
NC
18 P84/INT2
P30/A8(/-/D7) 63
NC
NC
19 P83/INT1
VCC 62
VCC
NC
20 P82/INT0
P31/A9 61
AMP_SW_MUTE
NC
21 P81/TA4IN/U
P32/A10 60
AMP_SW_PWR_
DWN
ENH_MRREQ
22 P80/TA4OUT/U
P33/A11 59
S_MUTE
DIR_GPO0
23 P77/TA3IN
P34/A12 58
NC
DIR_GPO1
24 P76/TA3OUT
P35/A13 57
AMP_SP_RELAY
DIR_RESET
25 P75/TA2IN/W
P36/A14 56
NC
DB_SCP_BSY
26 P74/TA2OUT/W
P37/A15 55
NC
DB_SCP_IRQ
27
P40/A16 54
NC
DOLBY_RESET
28
P72/CLK2
TA1OUT/V
P41/A17 53
NC
DIR_SCL/AD_SC
L/ENH_SCL
29
P71/RXD2/SCL
TA0IN/TB5IN
P42/A18 52
NC
DIR_SDA/AD_SD
A/ENH SDA
30
P70/TXD2/SDA
TA0OUT
P43/A19 51
AMP_SW_PROT
P
67/
T
X
D
1
P
6
6
/RX
D1
P
65/
C
LK
1
P
63/
T
X
D
0
P
6
2
/RX
D0
P
61/
C
LK
0
P
57/
R
D
Y
/C
LK
OU
T
P
56/
A
LE
P
55/
H
O
LD
P
5
4
/HL
DA
P
53/
B
C
LK
P
52/
R
D
P
51/
W
R
H
/B
H
E
P
50/
W
R
L/
W
R
P
47/
C
S
3
P
46/
C
S
2
P
45/
C
S
1
P
44/
C
S
0
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
FLASH_TXD/FL
D DAT
A
FLASH_RXD
FLASH
_
SCLK/F
LD
SCK
FLASH_BUSY/F
LD CS
DB_SDA
DB_SCL
ENH_RSTB
ENH_PWDB
OSC_OUT
ENH_BUSY
FLASH_EPM
EEP_SDA
EEP_SCL
NC
EEP-WP
FLASH_CE
NC
SW_VOL_CLK
SW_VOL_DATA
FLD RESET
P
64/
C
T
S
1/
R
T
S
1
/C
TS0
/C
L
KS1
P
60/
C
T
S
0/
R
T
S
0
IXA105AW
P73/CTS2/RTS2
TA1IN/V
AN-PR1100H
7 – 4
ICA1 VHiWM8775++-1: A/D Convertor (WM8775)
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Pin No.
Terminal Name
Input/Output
Function
1
AIN1L
Input
Channel 1 left input multiplexer virtual ground.
2
BCLK
Input/Output
ADC audio interface bit clock.
3
MCLK
Input
Master ADC clock: 256, 384, 512 or 768 fs (fs = Word clock frequency).
4
DOUT
Output
ACC data output.
5
ADCLRC
Input/Output
ADC left/right word clock.
6
DGND
—
Digital negative power supply.
7
DVDD
—
Digital positive power supply.
8
MODE
Input
Serial interface mode select.
9
CE
Input
Serial interface latch signal.
10
DI
Input/Output
Serial interface data.
11
CL
Input
Serial interface clock.
12*
NC
—
No connection.
13
VMIDADC
Output
ADC mid-rail divider decoupling pin: 10 µF external decoupling.
14
ADCREFGND
—
ADC negative power supply and PWB connection.
15
ADCREFP
Output
ADC positive reference decoupling pin: 10 µF external decoupling.
16
AVDD
—
Analog positive power supply.
17
AGND
—
ADC negative power supply and PWB connection.
18
AINVGR
Input
Right channel multiplexer ground.
19
AINOPR
Output
Right channel multiplexer output.
20
AINVGL
Input
Left channel multiplexer ground.
21
AINOPL
Output
Left channel multiplexer output.
22
AIN4R
Input
Channel 4 right input multiplexer ground.
23
AIN4L
Input
Channel 4 left input multiplexer ground.
24
AIN3R
Input
Channel 3 right input multiplexer ground.
25
AIN3L
Input
Channel 3 left input multiplexer ground.
26
AIN2R
Input
Channel 2 right input multiplexer ground.
27
AIN2L
Input
Channel 2 left input multiplexer ground.
28
AIN1R
Input
Channel 1 right input multiplexer ground.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AIN1L
BCLK
MCLK
DOUT
ADCLRC
DGND
DVDD
MODE
CE
DI
CL
NC
VMIDADC
ADCREFGND
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AIN1R
AIN2L
AIN2R
AIN3L
AIN3R
AIN4L
AIN4R
AINOPL
AINVGL
AINOPR
AINVGR
AGND
AVDD
ADCREFP
Figure 7-2 BLOCK DIAGRAM OF IC
AN-PR1100H
7 – 5
ICM3 VHiCS8416CN-1: DIR (CS8416CN)
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Pin No.
Terminal Name
Function
1*
RXP3
Positive AES3/SPDIF input (Input) - Single-ended/differential receiver inputs carrying AES3 or S/PDIF 
coded digital data.
2
RXP2
3
RXP1
4
RXP0
5
RXN
Negative AES3/SPDIF input (Input) - Single-ended/differential receiver inputs carrying AES3 or S/PDIF 
coded digital data.
6
VA
Analog power supply (Input) - Analog power supply. + 3.3 V normally.
7
AGND
Analog ground (Input) - Ground for chip analog circuit.
8
FILT
PLL loop filter (Output) - RC network is connected between this pin and the analog ground.
9
RST
Reset (Input) - When RST is low, CS8416 enters the low power mode and every internal state is reset.
10*
RXP4
Positive AES3/SPDIF input (Input) - Single-ended/differential receiver inputs carrying AES3 or S/PDIF 
coded digital data.
11*
RXP5
12*
RXP6
13*
RXP7
14
AD0/CS
Address bit (I
2
C)/control port chip select (SPI) (Input) - On the falling edge of this pin, CS8416 enters the 
SPI control port mode. In a position other than the falling edge, SC8416 enters the default I
2
C mode.
15
AD1/CDIN
Address bit (I
2
C)/ serial control data input (Input). In the I
2
C mode, AD1 is a chip address pin.
16
SCL/CCLK
Control port clock (Input). Serial control interface clock is used for clock control of data bit in or from CS 
8416.
17
SDA/CDOUT
Serial control data input/output (I
2
C)/data output (SPI) (input/output). In the I
2
C mode, SDA is a control 
input/output data line.
18
AD2/GPO2
Output 2 (Output). When using the I
2
C control port, 45 k
Ω. resistor makes this pin high or low.
19
GPO1
Output 1 (Output).
20
GPO0
Output 0 (Output).
21
VL
Logic power supply (Input) - Input/output power supply. + 3.3 V or 5.0 V normally.
22
DGND
Digital and input/output ground (Input) - Ground for input/output and core logic.
23
VD
Digital power supply (Input). Digital core power supply. + 3.3 V normally.
24
RMCK
Input select recovered master clock (Output). Input select recovered master clock output from PLL.
25
OMCK
System clock (Input) - When the OMCK system clock mode is active by using SWCLD bit of the control 1 
register, clock signal input of this pin is automatically output via RMCK of PLL unlock.
26
SDOUT
Serial audio output data (Output) - Audio data serial output pin.
27
OSCLK
Serial audio output bit clock (Input/output) - Serial bit clock for audio data of SDOUT pin.
28
OLRCK
Serial audio output left/right clock (Input/output) - Word-rate clock for audio data of SDOUT pin.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
RXP3
RXP2
RXP1
RXP0
RXN
VA
AGND
FILT
RST
RXP4
RXP5
RXP6
RXP7
AD0/CS
28
27
26
25
24
23
22
21
20
19
18
17
16
15
OLRCK
OSCLK
SDOUT
OMCK
RMCK
VD
DGND
VL
GPO0
GPO1
AD2/GPO2
SDA/CDOUT
SCL/CCLK
AD1/CDIN
Figure 7-3 BLOCK DIAGRAM OF IC
AN-PR1100H
7 – 6
ICM6 VHiCS49510+-1: DSP (CS49510) (1/3)
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Pin No.
Terminal Name
Default Function
Secondary Description
1*
GPIO28
Input/Output
Channel status word clock input.
2
GPIO29
Input/Output
1. Channel status data input.
2. SPDIF pass-through input.
3*
DBDA
Debug data
Debug data.
4*
DBCK
Debug clock
Debug clock.
5*
GPIO21
General-purpose input/output
1. Serial PCM audio data output synchronized with DAO2_SCLK/
DAO2_LRCLK (Pin 14).
2. IEC60958/61397 type 2-phase mark coded SPDIF data.
6*
GPIO20
General-purpose input/output
1. Serial PCM audio data output synchronized with DAO2_SCLK/
DAO2_LRCLK.
2. EEPROM boot chip select.
7*
GPIO19
General-purpose input/output
Serial PCM audio data output synchronized with DAO2_SCLK/
DAO2_LRCLK.
8
DAO_MCLK
Audio master clock
Audio master clock.
9
TEST
Test
Test
10
VDDD1
Core power supply voltage
Core power supply voltage.
11
GPIO18
General-purpose input/output
1. Serial PCM audio data output synchronized with DAO2_SCLK/
DAO2_LRCLK.
2. Hardware strap mode select.
12*
GPIO22
General-purpose input/output
Serial PCM audio bit clock for serial data pin.
(DAO2_DATA0, DAO2_DATA1, DAO2_DATA2, DAO2_DATA3)
13
GNDD1
Core ground
Core ground.
14*
GPIO23
General-purpose input/output
Serial PCM audio sample rate for serial data pin.
(DAO2_DATA0, DAO2_DATA1, DAO2_DATA2, DAO2_DATA3)
15*
GPIO17
General-purpose input/output
1. Digital audio output 4.
2. S/PDIF audio A.
16
GPIO16
General-purpose input/output
1. Digital audio output 3.
2. Hardware strap mode select.
17
GPIO15
General-purpose input/output
1. Digital audio output 2.
2. Hardware strap mode select.
18
VDDIO1
Input/output power supply voltage
Input/output power supply voltage.
19
DAO1_DATA0
Digital audio output 1
Hardware strap mode select.
20
DAO1_SCLK
PCM audio output bit clock
PCM audio output bit clock.
21
GNDIO1
Input/output ground
Input/output ground.
22
DAO1_LRCLK
Audio output sample rate (left/
right) clock
Audio output sample rate (left/right) clock.
23*
GPIO31
General-purpose input/output
UART clock.
24
VDDD2
Core power supply voltage
Core power supply voltage.
25*
GPIO25
General-purpose input/output
UART output.
26*
GPIO24
General-purpose input/output
UART input.
27
GNDD2
Core ground
Core ground.
28*
SD_DQM0#
SDRAM data mask 0
SDRAM data mask 0.
29*
SD_D7
SRAM data bit 7
SRAM data bit 15.
30*
SD_D6
SRAM data bit 6
SRAM data bit 14.
31*
SD_D5
SRAM data bit 5
SRAM data bit 13.
32*
SD_D4
SRAM data bit 4
SRAM data bit 12.
33
VDDIO2
Input/output power supply voltage
Input/output power supply voltage.
34*
SD_D3
SRAM data bit 3
SRAM data bit 11.
35*
SD_D2
SRAM data bit 2
SRAM data bit 10.
36
GNDIO2
Input/output ground
Input/output ground
37*
SD_D1
SRAM data bit 1
SRAM data bit 9.
38*
EXT_WE#
SDRAM write enable
SDRAM write enable.
39*
SD_D0
SRAM data bit 0
SRAM data bit 8.
40*
SD_D15
SRAM data bit 15
SRAM data bit 7.
41*
SD_D14
SRAM data bit 14
SRAM data bit 6.
42*
SD_D13
SRAM data bit 13
SRAM data bit 5.
43*
SD_D12
SRAM data bit 12
SRAM data bit 4.
44
VDDIO3
Input/output power supply voltage
Input/output power supply voltage.
45*
SD_D11
SRAM data bit 11
SRAM data bit 3.
46*
SD_D10
SRAM data bit 10
SRAM data bit 2.
47
GNDIO3
Input/output ground
Input/output ground
48*
SD_D9
SRAM data bit 9
SRAM data bit 1.
49*
SD_D8
SRAM data bit 8
SRAM data bit 0.
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