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Model
AN-PR1100H
Pages
108
Size
14.32 MB
Type
PDF
Document
Service Manual
Brand
Device
Audio / Home Theatre
File
an-pr1100h.pdf
Date
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Sharp AN-PR1100H Service Manual ▷ View online

AN-PR1100H
7 – 7
ICM6 VHiCS49510+-1: DSP (CS49510) (2/3)
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Pin No.
Terminal Name
Default Function
Secondary Description
50*
SD_DQM1# 
SDRAM data mask 1
SDRAM data mask 1.
51*
SD_CLKOUT
SDRAM clock output
SDRAM clock output.
52
SD_CLKIN
SDRAM clock input
SDRAM clock input.
53*
SD_CLKEN
SDRAM clock enable
SDRAM clock enable.
54
VDDD3
Core power supply voltage
Core power supply voltage.
55*
SD_A12
SRAM address bit 12
SRAM address bit 12.
56*
SD_A11
SRAM address bit 11
SRAM address bit 11.
57
GNDD3
Core ground
Core ground.
58*
SD_A9
SRAM address bit 9
SRAM address bit 9.
59*
SD_A8
SRAM address bit 8
SRAM address bit 8.
60
VDDIO4
Input/output power supply voltage
Input/output power supply voltage.
61*
SD_A7
SRAM address bit 7
SRAM address bit 7.
62*
SD_A6
SRAM address bit 6
SRAM address bit 6.
63
GNDIO4
Input/output ground
Input/output ground.
64*
SD_A5
SRAM address bit 5
SRAM address bit 5.
65*
EXT_CS2#
SRAM chip select 2
SRAM chip select 2.
66
VDDD4
Core power supply voltage
Core power supply voltage.
67*
SD_A4
SRAM address bit 4
SRAM address bit 4.
68*
SD_A3
SRAM address bit 3
SRAM address bit 3.
69
GNDD4
Core ground
Core ground.
70*
SD_A2
SRAM address bit 2
SRAM address bit 2.
71*
SD_A1
SRAM address bit 1
SRAM address bit 1.
72*
SD_A0
SRAM address bit 0
SRAM address bit 0.
73
VDDIO5
Input/output power supply voltage
Input/output power supply voltage.
74*
SD_A10
SRAM address bit 10
SRAM address bit 10.
75*
SD_A14
SRAM address bit 14
SRAM address bit 14.
76
GNDIO5
Input/output ground
Input/output ground.
77*
SD_A13
SRAM address bit 13
SRAM address bit 13.
78*
SD_WE#
SDRAM write enable
SDRAM write enable.
79*
SD_CAS#
SDRAM column address strobe
SDRAM column address strobe.
80*
SD_RAS#
SDRAM low address strobe
SDRAM low address strobe.
81*
SD_CS#
SRAM chip select
SRAM chip select.
82*
EXT_A15
SRAM address bit 15
SRAM address bit 15.
83
VDDD5
Core power supply voltage
Core power supply voltage.
84*
EXT_A16
SRAM address bit 16
SRAM address bit 16.
85*
EXT_A17
SRAM address bit 17
SRAM address bit 17.
86
GNDD5
Core ground
Core ground.
87*
EXT_A18
SRAM address bit 18
SRAM address bit 18.
88*
EXT_A19
SRAM address bit 19
SRAM address bit 19.
89*
EXT_OE#
SDRAM output enable
SDRAM output enable.
90*
EXT_CS1#
Active low chip select for SRAM 
mode
Active low chip select for SRAM mode.
91
VDDIO6
Input/output power supply voltage
Input/output power supply voltage.
92
GPIO30
Input/Output
1. Channel status user data input.
2. SPDIF pass-through input.
93
RESET#
Chip reset
Chip reset.
94
GNDIO6
Input/output ground
Input/output ground.
95*
GPIO33
Input/Output
SPI mode master data output/ slave data input.
96*
GPIO32
Input/Output
SPI chip select.
97
GPIO34
Input/Output
1. SPI mode master data output.
2. I
2
C mode master/slave data input/output.
98
VDDD6
Core power supply voltage
Core power supply voltage.
99
GPIO35
Input/Output
SPI/I
2
C control port clock.
100
GPIO36
Input/Output
Serial control port data ready interrupt request.
101
GNDD6
Core ground
Core ground.
102
GPIO37
Input/Output
1. Serial control port 1 input busy.
2. Parallel control port input busy.
103
GPIO38
Input/Output
1. Parallel port write select.
2. Parallel port data strobe.
3. SPI/I
2
C control port clock.
AN-PR1100H
7 – 8
ICM6 VHiCS49510+-1: DSP (CS49510) (3/3)
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Pin No.
Terminal Name
Default Function
Secondary Description
104*
GPIO39
Input/Output
1. Parallel port chip select.
2. SPI chip select.
105
GPIO11
Input/Output
1. Parallel control port address bit 3.
2. Parallel control port address strobe.
3. SPI mode master data input /slave data output.
4. I
2
C mode master/slave data input/output.
106*
GPIO10
Input/Output
1. Parallel control port address bit 2.
2. Parallel control port address bit 10.
3. SPI mode master data output /slave data input.
107*
GPIO40
Input/Output
1. Parallel read select.
2. Parallel read/write select.
108*
GPIO41
Input/Output
1. Parallel control port data ready interrupt request.
2. Serial control port data ready interrupt request.
109*
GPIO9
Input/Output
1. Parallel control port address bit 1.
2. Parallel control port address bit 9.
110*
GPIO8
Input/Output
1. Parallel control port address bit 0.
2. Parallel control port address bit 8.
111*
GPIO7
Input/Output
1. Parallel control port data bus.
2. Parallel control port multiplex address and data bus.
112*
GPIO6
Input/Output
1. Parallel control port data bus.
2. Parallel control port multiplex address and data bus.
113
VDDIO7
Input/output power supply voltage
Input/output power supply voltage.
114*
GPIO5
Input/Output
1. Parallel control port data bus.
2. Parallel control port multiplex address and data bus.
115*
GPIO4
Input/Output
1. Parallel control port data bus.
2. Parallel control port multiplex address and data bus.
116
GNDIO7
Input/output ground
Input/output ground.
117*
GPIO3
Input/Output
1. Parallel control port data bus.
2. Parallel control port multiplex address and data bus.
118*
GPIO2
Input/Output
1. Parallel control port data bus.
2. Parallel control port multiplex address and data bus.
119
VDDD7
Core power supply voltage
Core power supply voltage.
120*
GPIO1
Input/Output
1. Parallel control port data bus.
2. Parallel control port multiplex address and data bus.
121*
GPIO0
Input/Output
1. Parallel control port data bus.
2. Parallel control port multiplex address and data bus.
122
GNDD7
Core ground
Core ground.
123
XTAL_OUT
Buffered reference clock input/
crystal oscillator input
Buffered reference clock input/crystal oscillator input.
124
XTI (4)
Reference clock input/crystal 
oscillator input
Reference clock input/crystal oscillator input.
125
XTO (4)
Crystal oscillator output 1
Crystal oscillator output 1.
126
GNDA
PLL ground
PLL ground.
127
FILT2
Phase lock loop filter for PLL
Phase lock loop filter for PLL.
128
FILT1
Phase lock loop filter for PLL
Phase lock loop filter for PLL.
129
VDDA
PLL power supply
PLL power supply.
130
VDDD8
Core power supply voltage
Core power supply voltage.
131
GPIO14
Input/Output
PCM audio input data 3.
132
GPIO13
Input/Output
PCM audio input data 2.
133
GNDD8
Core ground
Core ground.
134
GPIO12
Input/Output
PCM audio input data 1.
135*
DAI1_DATA0
PCM audio input data 0
PCM audio input data 0.
136
VDDIO8
Input/output power supply voltage
Input/output power supply voltage.
137*
DAI1_SCLK
PCM audio input bit clock
PCM audio input bit clock.
138*
DAI1_LRCLK
PCM audio input sample rate 
(left/right) clock
PCM audio input sample rate (left/right) clock.
139
GNDIO8
Input/output ground
Input/output ground.
140
GPIO42
Input/Output
1. PCM audio input sample rate (left/right) clock.
2. Compressed audio input request.
3. Parallel control port data ready interrupt request.
4. Parallel control port input busy.
141
GPIO43
Input/Output
1. PCM audio input bit clock.
2. Audio input bit clock.
142
DAI2_DATA4
PCM Audio input data
Audio input data.
143*
GPIO27
Input/Output
SPDIF receiver unlock interrupt input.
144*
GPIO26
Input/Output
Brick interrupt input.
AN-PR1100H
7 – 9
GPIO1, PCP_AD1 / D1
GPIO0, PCP_AD0 / D0
G
P
IO
2
5
,
U
A
R
T_
TX
D
GPI
O2
4,
U
A
R
T
_R
XD
GP
IO
31
,
U
A
R
T
_
C
L
K
XTO
VDD7
GND7
VDDIO7
XTI
GNDIO7
GNDA
FILT2
FILT1
VDDA
VDD8
GND8
GPIO13, DAI1_DATA2, TM2
GPIO14, DAI1_DATA3, TM3
DAI1_DATA0, TM0
GPIO12, DAI1_DATA1, TM1
113
116
119
122
123
124
127
128
131
132
134
137
138
141
142
143
126
129
130
133
136
139
GPIO2, PCP_AD2 / D2
GPIO3, PCP_AD3 / D3
GPIO4, PCP_AD4 / D4
GPIO5, PCP_AD5 / D5
GPIO6, PCP_AD6 / D6
GPI
O3
9,
PC
P
_
C
S
#
,
SC
P
2
_C
S#
GPIO7, PCP_AD7 / D7
GPIO9, PCP_A1 / A9
GPIO3
8,
P
C
P
_
W
R
#
/
D
S#,
SC
P
2
_C
LK
V
DD6
G
P
IO
4
0
,
P
CP
_
RD#
/
R
W#
G
ND6
G
P
IO
10
,
P
C
P
_A
2
/
A
1
0,
S
C
P
2
_M
O
S
I
GPI
O
4
1,
PC
P
_I
R
Q
#
,
SC
P
2
_I
RQ#
GPIO3
7,
SC
P
1
_BS
Y#,
P
C
P_BSY
#
V
DDI
O
6
G
P
IO
11
,
P
C
P
_A
3,
A
S
#,
S
C
P
2_
M
IS
O
/
S
D
A
G
NDI
O
6
GPOI3
6
,
S
C
P
1
_
IR
Q#
G
P
IO
3
4
,
S
C
P
1
_
_
M
IS
O
/
S
D
A
G
P
IO
33,
S
C
P1_
M
OSI
G
P
IO
35,
SCP1_C
LK
V
DD5
V
DDI
O
5
G
ND5
G
NDI
O
5
SD
_C
AS#
SD
_R
AS#
SD_A3, EXT_A3
SD_A2, EXT_A2
SD_A1, EXT_A1
SD_A0, EXT_A0
10
1
98
99
94
91
92
93
96
97
86
83
76
73
74
77
78
79
81
82
84
87
88
89
SD
_A10
,
EXT
_
A
1
2
SD_A11, EXT_A10
VDD4
GND4
SD
_C
S#
SD_A4, EXT_A4
SD_A5, EXT_A5
SD_A6, EXT_A6
SD_A7, EXT_A7
SD_A8, EXT_A8
SD_CLKEN
SD_A9, EXT_A9
VDDIO4
GNDIO4
SD_CLKOUT
SD_CLKIN
SD_D10, EXT_D2
SD_D11, EXT_D3
SD_D12, EXT_D4
VDD3
GND3
SD_D13, EXT_D5
SD_D14, EXT_D6
SD_D15, EXT_D7
SD_DQM1
SD
_D
7
,
EX
T
_
D
1
5
SD
_D
6
,
EX
T
_
D
1
4
VDDIO3
GNDIO3
SD
_D
5
,
EX
T
_
D
1
3
SD
_
D
Q
M
0
SD
_D
4
,
EX
T
_
D
1
2
SD
_D
3
,
EX
T
_
D
1
1
SD
_D
2
,
EX
T
_
D
1
0
69
66
63
60
61
62
64
67
68
57
54
47
44
1
2
3
4
6
7
8
GPIO26, CSW _BIRQ
GPI
O17
,
DAO1_
D
A
T
A3
/
X
MT
A
G
P
IO
1
5
,
D
AO
1
_
D
A
T
A1
,
H
S1
DA
O
1
_
DA
TA
0
,
HS
0
DA
O
1
_
L
RCL
K
DAI1_LRCLK
DA
O
_
MCL
K
G
P
IO
20,
D
AO2
_D
AT
A2,
EE_C
S#
DAI1_SCLK
V
DD1
G
ND1
DA
O
1
_
S
CL
K
GPI
O16
,
D
A
O
1_D
AT
A
2
,
H
S
2
GPIO23
,
D
A
O
2_L
R
C
LK
R
ESE
T
#
V
DDI
O
1
G
P
IO
22,
D
AO2
_SC
LK
G
NDIO
1
GPI
O18
,
D
A
O
2_D
AT
A
0
,
H
S
3
GPI
O19
,
D
AO2_
D
A
T
A1
V
DD2
G
ND2
GPI
O21
,
DAO2_
D
A
T
A3
/
X
M
T
B
V
DDI
O
2
G
NDI
O
2
SD
_WE#
SD_D0, EXT_D8
SD_D1, EXT_D9
5
9
10
11
12
14
16
17
19
20
22
23
26
28
29
31
32
34
13
18
21
24
27
33
36
SD_D8, EXT_D0
SD_D9, EXT_D1
SD_A12, EXT_A11
SD
_A13
,
EXT
_A14
SD
_A14
,
EXT
_
A
1
3
G
P
IO
3
2
,
S
CP
1
_
CS
#
,
IO
WA
IT
VDDIO8
GNDIO8
EX
T
_A15
EX
T
_A16
EX
T
_A17
EX
T
_A18
EX
T
_A19
E
X
T_
CS
1
#
GPIO8, PCP_A0 / A8
EXT_CS2#
EX
T
_OE#
EXT_W E#
GPIO27, CSW _ERR
G
P
IO
28,
CSW
_
C
L
K/
DDAC
GPI
O29
,
C
SW_C,
XM
TA
_
IN
G
P
IO
30,
CSW_U
,
X
M
T
B_I
N
TE
S
T
DB
DA
DB
CK
XTAL_OUT
GPIO43, BDI_CLK, DAI2_SCLK
DI_REQ# , DAI2_LRCLK, PCP_IRQ# / BSY#
BDI_DATA, DAI2_DATA
15
25
30
35
37
38
39
41
42
43
46
48
49
40
45
50
51
52
53
55
56
58
59
65
70
71
72
75
80
85
90
95
10
102
103
104
106
107
0
10
5
10
8
109
11
111
112
114
117
118
121
0
115
120
125
135
140
144
Figure 7-4 BLOCK DIAGRAM OF IC
AN-PR1100H
7 – 10
ICM10 VHiLC750512-1: Audio Enhancer (LC750512) (1/2)
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Pin No.
Terminal Name
Input/Output
Function
1
PLLPWRR
Input
Power ring for PLL (ESD) (+1.8 V).
2
PLLGNDR
—
GND for PLL (ESD).
3
PLLAVDD
Input
Power supply for PLL (+1.8 V).
4
PLLAVSS
—
GND for PLL.
5
PLLDVDD
Input
Digital power supply for PLL (+1.8 V).
6
PLLDVSS
—
Digital GND for PLL (ESD).
7
TEST2
Input
Test terminal.
8
TEST3
Input
Test terminal.
9
DVSS4
—
Digital GND.
10
DVDD4
Input
Digital power supply (+1.8 V).
11
XVSS
—
GND for crystal.
12
XOUT
Output
Crystal oscillating output.
13
XIN
Input
Crystal oscillating input.
14
XVDD
Input
Power supply for crystal (+3.3 V).
15
CVDD4
Input
Digital power supply (+3.3 V).
16
CVSS4
—
Digital GND.
17
TEST0
Input
Test terminal.
18
TEST1
Input
Test terminal.
19
TEST4
Input
Test terminal.
20
TEST5
Input
Test terminal.
21
BVSS1
—
Logic GND in analog chip.
22
BVDD1
Input
Logic power supply in analog chip (+3.3 V).
23
AVSS4
—
DAC analog GND.
24
AVDD4
Input
DAC analog VDD (+5 V).
25
AVDD3
Input
EVR analog VDD (+5 V).
26
AVSS3
—
EVR analog GND.
27
AOUT1
Output
Lch EVR output.
28
EVRINL
Input
Lch EVR input.
29
DAOUTL
Output
Lch DAC analog output.
30
DAOUTR
Output
Rch DAC analog output.
31
EVRINR
Input
Rch EVR input.
32
AOUT2
Output
Rch EVR output.
33
AVSS2
—
GND for VREF.
34
AVDD2
Input
VDD for VREF (+5 V).
35
VREF2
Output
Reference voltage output terminal 2 (DAC, EVR).
36
VREF1
Output
Reference voltage output terminal 1 (ADC).
37
INL
Input
Lch ADC analog input.
38
INR
Input
Rch ADC analog input.
39
AVSS1
—
ADC analog GND.
40
AVDD1
Input
ADC analog power supply (+5V)
41*
TEST6
Input/Output
Test terminal.
42
XSEL0
Input/Output
Crystal frequency setting signal 0.
43
XSEL1
Input/Output
Crystal frequency setting signal 1.
44
XSEL2
Input/Output
Crystal frequency setting signal 2.
45
CVSS1
—
Digital GND.
46
CVDD1
Input
Digital power supply (+3.3 V).
47
LRCKI
Input
LR clock input.
48
BCKI
Input
Bit clock input.
49
DATAI
Input
Data input.
50
SCKII
—
External clock input.
51
DVSS1
—
Digital GND.
52
DVDD1
Input
Digital power supply (+1.8V).
53*
SCKO
Output
DAC master clock output.
54
TEST7
Input
Test terminal.
55*
DATAO2
Output
Data output 2.
56*
DATAO1
Output
Data output 1.
57*
DATAO0
Output
Data output 0.
58*
BCKO
Output
Bit clock output.
59*
LRCKO
Output
LR clock output.
60
CVSS2
—
Digital GND.
61
CVDD2
Input
Digital power supply (+3.3 V).
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