Panasonic KX-TCD961GB Service Manual ▷ View online
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KX-TCD961GB
Fig. 33
1.6 AUDIO PATH - TX AUDIO (SEE Fig. 33)
Balanced audio from the microphone (TP40 and TP41) enters the BBIC at pins 61 and 63. A balanced bias voltage for
the (“electret” type) microphone is supplied by the BBIC from pins 60 and 64 via R31 and R32. This supply is
de-coupled by R22, R27, C21, C28, and C22. RF de-coupling of the microphone signal is provided by R27, C25, R28,
C26, R24, R25, and C20.
The microphone audio signals are coupled to the BBIC via C22 and C23, which provide some high pass filtering.
In the BBIC audio passes through the gain-controlled microphone amplifier, into the ADC part of the codec, where it is
sampled and turned into digital data. The burst mode controller then processes this raw data (called the B-field)
performing encryption and scrambling, adding the various other fields that go together to produce the GAP standard
DECT frame, assigning to a time slot and channel etc. The data then passes through the gaussian filter to emerge on
pin 20 as TRADAT.
1.7 AUDIO PATH - RX AUDIO (SEE Fig. 33)
Audio from the receiver RECDAT (TP54) enters the BBIC on pin 18 and passes through the clock recovery circuit. The
burst mode controller separates out the B-field data, and performs de-encryption and de-scrambling as required. It
then goes to the DAC part of the codec where data is turned back into analogue audio. The audio signal is
amplified by the gain-controlled earpiece amplifier, and balanced audio is output on pins 65 and 66, and fed to the
earpiece (TP31 and TP32). The leads feeding the earpiece are RF de-coupled by C15 to R22, C17, C16, R23, and
C18. C19 provides low pass filtering.
Circuit Diagram
DAC
CODEC
ADC
B.M.C.
GAUSS FILTER
RSSI ADC
CLOCK/DATA
RECOVERY
RECOVERY
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1.8 CLOCK GENERATION (SEE Fig. 33)
A single clock generator in the BBIC uses an external crystal X1 to derive all clock frequencies used in the handset.
The crystal is tuned to the exact frequency of 10.368 MHz during manufacture by feeding a DC voltage from an
internal DAC (from pin 12) to the varicap diode D12 (TP25). The RFCLK output (pin 10, TP56) is a buffered clock
signal at 10.368 MHz for the Frequency Synthesizer, that is only active during the PLL lock period (see section 1.3).
The basic data rate for TX-DATA and RX-DATA is 1.152 Mbits/s, which is divided by 9. The data rate for the serial
interface to the phase-lock-loop is also 1.152 Mbits/s.
1.9 KEYBOARD (SEE Fig. 34)
The keyboard “On” button is connected directly to pin 41 of the BBIC (TP10). When pressed it turns the handset on
and off (must be held for off). All other keys are connected in a row/column matrix. They are scanned in six rows using
scan pulses (only active when keys are pressed) from IC1 pins 28 to 33. The four key matrix columns are input to the
BBIC on pins 31 to 34.
Fig. 34
Circuit Diagram
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1.10 FACTORY SERIAL PORT (SEE Fig. 31)
In order to communicate with the handset during manufacture and servicing (using a PC) a serial data link has been
provided. Serial data input/output is provided on J6 (TP65), and a ground is provided on J7. The bi-directional serial
data line is split into two at IC1 pin 27 (input) and pin 26 (output). Data rate is 9600 baud or 115.2 kBaud.
D13 provides ESD protection, and R37 and C56 provide RF de-coupling.
1.11 BUZZER CIRCUIT (SEE Fig. 35)
A square-wave signal from IC1 pin 45 is used to sound the buzzer via switching transistor T5 (TP22). Various tones
and cadences are used dependent on function. Buzzer volume is varied by changing the duty cycle of the drive
waveform. D11 provides quenching of back-emf generated when T5 turns off.
1.12 BATTERY SUPPLY (SEE Fig. 35)
The three cell NiCd/NiMH rechargeable battery supplies the handset via 2A fuse (actually a coil), and is de-coupled by
C3 and C4. It directly supplies T3 in the baseband section, and also the Tx PA in the RF Section. It also supplies IC1
(de-coupled by C9), and most of the RF Section (VCC-OC) (decupled by R35 and C47, C48 and VCC-PA).
1.13 MAIN 3V REGULATOR (SEE Fig. 35)
The BBIC measures the battery voltage on pins 58 using an internal ADC. If the battery voltage is below 3.36 V, TC3 is
switched to power off mode. R7 and C5 provide a reset pulse (TP84) used for resetting the BBIC when power on.
The +3 V supply (TP10) is fed to the BBIC, Flash PROM, EEPROM, and Display Driver.
1.14 BATTERY CHARGING CIRCUIT (SEE Fig. 35)
The charge circuit is designed to operate with a constant current charger in the base. L1, L2, D2 and D4 protect
against electro-static discharge (ESD). The charging current from the base is turned on and off by T1 using a control
signal from the BBIC (pin 39, TP6) via T2. R3 provides initial current in the event of a totally flat battery, and D6 pro-
tects against the high voltage present on the charge contacts if there is no battery in the handset. R4 and R5 provide a
signal for the BBIC to detect (pin 40) that the handset had been placed on the base charger. If the handset is off, it will
be switched on, and charging will start.
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Fig. 35
Circuit Diagram
BUZZER
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