DOWNLOAD Panasonic AW-E800E Service Manual ↓ Size: 3.52 MB | Pages: 50 in PDF or view online for FREE

Model
AW-E800E
Pages
50
Size
3.52 MB
Type
PDF
Document
Service Manual
Brand
Device
Provideo / CAMERA
File
aw-e800e.pdf
Date
PREV: Panasonic AW-E650E / MC Service Manual

Panasonic AW-E800E Service Manual ▷ View online

– 10 –
R140
(INT 28M)
R190
 (Y-BLK)
R132
 (B-CB)
R188
(R-CB)
R192
(SC/H)
DSP BOARD
(PATTERN  SIDE)
ANALOG  PROCESS  BOARD
(PATTERN  SIDE)
TP5 (VD)
TP4 (HD)
TP6 (INT 28M)
ENCODER BOARD
(COMPONENT  SIDE)
DRIVE BOARD
(COMPONENT  SIDE)
(PATTERN  SIDE)
R3
(VSUB R)
E3
(VSUB R)
R2
 (VSUB G)
E2
 (VSUB G)
R1
 (VSUB B)
E1
 (VSUB B)
R61
(RG R)
E13
(RG R)
R59
(RG G)
E12
(RG G)
R57
(RG B)
E11
(RG B)
R113
(OG B)
E14
(OG B)
R116
(OG G)
E15
(OG G)
R119
(OG R)
E16
(OG R)
R767
(V TOP)
R760
(H TOP)
R646
(B-LEVEL)
R446
(G-LEVEL)
R246
(R-LEVEL)
R128
(R-DC)
R801
(R-V TOP)
R803
(G-V TOP)
R805
(B-V TOP)
R792
(R-H TOP)
R794
(G-H TOP)
R796
(B-H TOP)
R783
(R-H SAW)
R785
(G-H SAW)
R787
(B-H SAW)
R774
(R-H PARA)
R776
(G-H PARA)
R778
(B-H PARA)
R328
(G-DC)
R528
(B-DC)
R123
(R-WC)
R323
(G-WC)
R523
(B-WC)
E101
(R-IN)
E301
(G-IN)
E501
(B-IN)
E701 (GND)
E507
(B)
E502
E503
E504
E505
(B-OUT)
E305
(G-OUT)
E105
(R-OUT)
E304
E104
E303
E103
E302
E102
E307
(G)
E107
(R)
LOCATION OF TEST POINTS AND ADJUSTING CONTROLS
26
25
24
23
22
21
20
18
17
16
15
14
13
12
11
8
7
5
3
1
+7V IN
–12.5V IN
+7V IN
–12.5V IN
+7V IN
-12.5V IN
2GASO IN
SHT MASK IN
OBCP OUT
SLOAD IN
PBL OUT
SCLK IN
VD IN
SDATA IN
HD IN
CLK36M OUT
ADCLK OUT
+16.5V IN
+16.5V IN
+16.5V IN
+5V
19
83
PAL
NTSC
E501
(B-IN)
Q505-Q512
B CHANNEL
SAMPLE/HOLD
R523
(B-WCLP)
Q521
Q522
Q513-Q520
U501
SELECTOR
B CHANNEL
PREAMP
CF501
CF502
BUFFER
AMP
B-OUT
BUFFER
SHD
SHD
SHP
SHP
7
6
CH0
1
COM
A
5
E301
(G-IN)
Q301-Q312
G CHANNEL
SAMPLE/HOLD
R323
(G-WCLP)
Q321
Q322
Q313-Q320
U301
SELECTOR
G CHANNEL
PREAMP
CF301
CF302
BUFFER
BUFFER
SHD
SHP
7
6
CH0
CH1
1
COM
A
5
E101
(R-IN)
Q101-Q112
R CHANNEL
SAMPLE/HOLD
R123
(R-WCLP)
Q121
Q122
Q113-Q120
U101
SELECTOR
R CHANNEL
PREAMP
CF101
CF102
BUFFER
2GASO
BUFFER
SHD
SHP
7
6
CH0
CH1
1
COM
A
5
CH1
96
1
2
SLOAD
SCLK
SDATA
4
97
25
27
26
75
28
24
PC OUT
PNSW
XI
XO
X1
D6
U10
TIMING
GENERATOR
U11
U14
U15
U13
+7V
–12.5V
2
4
#2GASO
SHT MASK
1
1
2
4
2
4
7
6
5
SS3
SS2
SS1
U12
TO DSP
BOARD
...P5
1
2
4
CPOB
FHS
PBLK
EXVD
FCK
ADCLK
EXHD
HD2
+16.5V
+7V
+5V
+5V
REG
+16.5V
+16V
+16V
REG
–12.5V
–12V
–12V
REG
–11V
–11V
REG
U7(c),Q14,Q15
U7(b),Q12,Q13
U7(a),Q8,Q9
U7(d),Q10,Q11
D2
CP2
Q2
#Q2
D2
CP2
Q2
#Q2
U1(d)
U4(a)
U6(b)
U4(b)
U4(e)
U1(b)
U2(e)
U2(f)
U1(a)
U2(a)
U2(b)
U2(c)
U4(c)
12
13
11
U4(d)
9
8 11
12
23
22
9
8
#SD2
#CD2
5
10
13
6
6
7
14
13
4
3
4
5
6
#2GASO
85
84
12
11
9
8
D1
CP1
Q1
#Q1
U3(a)
#SD1
#CD1
2
4
3
2
3
4
18
17
16
U2(d)
5
15
1
11
10
#2GASO
2
3
5
6
DS2
DS1
1
2
1
U4(f)
U1(c)
88
91
90
68
50-57
69
72
D1
CP1
Q1
#Q1
U6(a)
Q19,Q20
Q16
R57
RG B
R59
RG G
R61
RG R
E11(RG B) E12(RG G) E13(RG R)
#SD1
#CD1
10
4
8
9
13
12
#2GASO
2
3
5
6
R
CH1
CH2
H2
H1
1
2
1
2
4
4
SUB
1
DRIVER
LEVEL
CLAMPER
Q17
LEVEL
CLAMPER
Q18
LEVEL
CLAMPER
Q4-Q7
Q1
U8
U9
R1
SUB B
R2
SUB G
R3
SUB R
E1(B)
E2(G)
E3(R)
DRIVER
LEVEL
CLAMPER
E14
R113
R116
R119
Q2
LEVEL
CLAMPER
Q3
LEVEL
CLAMPER
E15
E16
VA1
I
VA8
SHT MASK
26
24
22
20
19
18
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
26
24
22
20
19
18
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
SUB B
SUB G
SUB R
OG B
OG G
OG R
+16.0V
+16.0V
+5.0V
+5.0V
–12.0V
–11.0V
V1 OUT
V2 OUT
V3 OUT
V4 OUT
V5 OUT
V6 OUT
V7 OUT
V8 OUT
CH1 OUT
CH2 OUT
14
12
10
8
6
3
1
RG B
RG G
RG R
H1
H2
SHD
SHP
14
12
10
8
6
3
1
1
3
5
8
10
1
3
5
8
10
CCD B
CCD G
CCD R
SHD
SHP
+16V
+5V
–12V
–11V
E507
Q523
Q524
Q545
AMP
G-OUT
E307
Q323
Q324
Q345
AMP
R-OUT
E107
Q123
Q124
Q146
R528
R328
R128
R246
R446
R646
RCH SENSOR  BOARD  ASS'Y
GCH SENSOR  BOARD  ASS'Y
BCH SENSOR  BOARD  ASS'Y
TO / FROM
ANALOG
PROCESS
BOARD(2/2)
DRIVE  BOARD
ANALOG  PROCESS  BOARD (1/2)
HEAD
OPTICAL
ASS'Y
BLOCK  DIAGRAM  OF  DRIVE  BOARD / ANALOG  PROCESS  BOARD (1/2)
P3
P1
P1
P2
P2
P1
– 11 –
B-OUT
2GASO IN
G-OUT
R-OUT
B-PED IN
B-GAIN IN
G-PED IN
R-PED IN
R-GAIN IN
+7V IN
HEAD SEL IN
+7V IN
NSP2
+7V IN
AGC IN
+7V IN
–5V IN
+4.0V OUT
–5V IN
OBCP IN
–5V IN
+2V OUT
CP IN
PBLK IN
VD IN
AWCCONT IN
SWCOMMON OUT
NPS3
DADT IN
MACLK IN
KEY OUT
MADI IN
DACK IN
MACSLD IN
DACS IN
MADO OUT
5
6
9
13
31
32
33
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
P2
TO/FROM
ANALOG
PROCESS
BOARD
(1/2)
#B-PED
#B GAIN
#G-PED
R-PED
R GAIN
+7V
AGC
–5V
+4V
#BAGCS
#GAGCS
U1(c)
OB
R-IN
G-IN
B-IN
2GASO
CP1
#VDB
7
6
U1(d)
U1(a)
CP0
9
10
3
2
U1(b)
PB
5
4
U1(e)
14
15
+2V
RAGCS
DADT
MACLK
MADI
DACK
MACSLD
DACS
MADO
KEY
SWCOMMON 
AMP
R-IN
U102(b),U104(b)
Q125,Q126
U102(a)
E102(R GAIN-1)
U103
SELECTOR
U104(a),U105(a)
Q128-Q132
E103(R GAIN-2)
U107(b)
Q141-Q144
E105(R GAMMA)
PB
12
13
11
4
9
3
14
GAIN CONTROL
5
15
10
2
1
RS
RPUL
SHT=''H''
AMP
#GS
#BS
AGC
PEDESTAL
LEVEL
CONTROL
RGAIN
RGIN2
U105(b)
U107(a)
Q133
CP0
R-PED
RPED2
7
6
PB
+0.5V
5
PRE GAMMA
1
U106
SELECTOR
Q134-Q140
#B
A
C
D
CP0
R OUT
AMP
2
MADI
DADT
MACLK
DACS
MADO
DACK
MACSLD
1
3
U707(a)
1
7
2
U708(a)
6
3
5
U708(b)
U706
PEDESTAL/GAIN
S701
S702
S703
S704
9
10
8
U707(c)
13
12
11
U707(d)
DI
CLK
#CS/LD
DO
AO1
AO2
AO3
AO4
AO5
AO6
AO7
AO8
AO9
AO10
AO11
AO12
RPUL
MENU
SWCOMMON
VOLTAGE
FOLLOWER
KEY
ITEM
YES
NO
RGIN2
RPED2
#GPUL
#GGIN2
#GPED2
#BPUL
#BGIN2
#BPED2
1
2
3
4
5
6
7
8
9
10
11
12
U709
GAIN CONTROL
DI
CLK
#CS/LD
DO
CLK
LD
20
19
18
AO1
AO2
AO3
AO4
AO5
AO6
AO7
AO8
AO9
AO10
AO11
AO12
E
CP1
F
G
1
2
3
4
5
6
7
8
9
10
11
12
20
19
18
17
+6.7V
REG
A
+6.7V
+4.5V
U705(c)
VOLTAGE DIVIDER
VOLTAGE
FOLLOWER
#B
U705(b)
VOLTAGE
FOLLOWER
C
U705(d)
VOLTAGE
FOLLOWER
D
U705(a)
+0.5V
AWC CONT
6
7
5
1
U704
SELECTOR
R CHANNEL PROCESS
AMP
G-IN
U302(b),U304(b)
Q325,Q326
U302(a)
E302(G GAIN-1)
U303
SELECTOR
U304(a),U305(a)
Q328-Q332
OB
E303(G GAIN-2)
U307(b)
Q341-Q344
E305(G GAMMA)
12
13
11
4
9
3
14
GAIN CONTROL
5
15
10
2
1
#GPUL
SHT=''H''
AMP
AGC
PEDESTAL
LEVEL
CONTROL
#GGIN2
U305(b)
U307(a)
Q333
CP0
#G-PED
#GPED2
7
6
5
PRE GAMMA
1
U306
SELECTOR
Q334-Q340
#B
A
C
D
CP0
G-OUT
AMP
G CHANNEL PROCESS
VOLTAGE REGULATOR
+7V
+4.5V
REG
U701(d)
Q703
+2V
REG
U702(a)
+2V
+0.5V
REG
U701(b)
Q704
+0.5V
+4V
REG
U702(b)
Q706
+4V
–4.6V
REG
–5V
U701(a)
Q702
+6.7V
+4.5V
–4.6V
AMP
B-IN
U502(b),U504(b)
Q525,Q526
U502(a)
E502(B GAIN-1)
U503
SELECTOR
U504(a),U505(a)
Q528-Q532
E503(B GAIN-2)
U507(b)
Q541-Q544
E505(B GAMMA)
Q707-Q709
Q721
U703(a)
Q710
12
13
11
4
9
3
14
GAIN CONTROL
5
15
10
2
1
#BPUL
SHT=''H''
AMP
AGC
PEDESTAL
LEVEL
CONTROL
#BGIN2
U505(b)
U507(a)
Q533
CP0
#B-PED
#BPED2
7
6
5
PRE GAMMA
1
U506
SELECTOR
Q534-Q540
#B
A
C
D
CP0
AMP
B CHANNEL PROCESS
#BGAIN
ANALOG  PROCESS  BOARD (2/2)
BLOCK  DIAGRAM  OF  ANALOG  PROCESS  BOARD (2/2)
F
OB
G
OB
E
TO
JOINT
BOARD
....P1
U701(c)
Q701
CLK
LD
DO
DELAY
#VDB
Q711,Q712
Q722,Q723
DELAY
Q714
Q727
R760
DELAY
AMP
U703(b)
Q713
AMP
U703(c)
Q726
Q724
Q725
AMP
AMP
U703(d)
Q718
Q719
R778
R787
R796
R805
R776
R785
R794
R803
R774
R783
R792
R801
Q720
AMP
BUFFER
#BS
BUFFER
RS
BUFFER
#GS
+0.5V
PB
+0.5V
PB
B-OUT
PB
PB
– 12 –
4
5
6
9
10
13
15
16
17
18
19
21
25
27
29
31
33
35
37
20
22
24
26
28
30
32
34
36
38
39
41
43
45
47
49
51
53
55
57
40
42
44
46
48
50
52
54
56
58
+2V
DR-Y IN
+4V
DY IN
DB-Y IN
FELD
CP OUT
FVD OUT
VCLR IN
FHD OUT
HCLR IN
CHARA IN
DSPBLK IN
DSPSYNC IN
FBLK OUT
FSYNC OUT
CSYNC OUT
VDN OUT
HDN OUT
BYD0 OUT
BYD1 OUT
BYD2 OUT
BYD3 OUT
BYD4 OUT
BYD5 OUT
BYD6 OUT
BYD7 OUT
BYD8 OUT
BYD9 OUT
RDY0 OUT
RDY1 OUT
RDY2 OUT
RDY3 OUT
RDY4 OUT
RDY5 OUT
RDY6 OUT
RDY7 OUT
RDY8 OUT
RDY9 OUT
YD0 OUT
YD1 OUT
YD2 OUT
YD3 OUT
YD4 OUT
YD5 OUT
YD6 OUT
YD7 OUT
YD8 OUT
YD9 OUT
+4V
AMP
30
1
2
12
26
15-19
22-25
15-19
22-26
2
4
RY0-RY9
1-10
RYIN0
I
RYIN9
COUT0
I
COUT9
YIN0
I
YIN9
Y0-Y9
13-22
BY0-BY9
23-32
+2V
CP2
+4V
+2V
+2V
R-Y
AMP
AMP
VRHF
D0
I
D8
D9
VRLF
VIN
CLK
VOLTAGE
FOLLOWER
+4V
AMP
30
1
2
12
+2V
CP2
+4V
+2V
Y
AMP
U4(b)
AMP
VRHF
D0
I
D9
VRLF
VIN
CLK
VOLTAGE
FOLLOWER
Q51
+4V
AMP
30
1
2
12
+2V
CP2
+4V
+2V
CLK
B-Y
AMP
AMP
VRHF
D0
I
D8
D9
VRLF
VIN
CLK
VOLTAGE
FOLLOWER
1
2
4
BY0-BY9
RY0-RY9
Y0-Y9
+4V
CP2
FVD
FHD
HCLR
FBLK
FSYNC
DSPBLK
DSPSYNC
#VCLR
#VDN
HDN
FELD
CSYNC
26
15-19
22-25
2
4
BCIN0
I
BCIN9
CP2
FELD
FVD
INVI3
VCLR
FWHD
INVI2
HCLR
DSPBLK
DSPSYNC
FBLK
FSYNC
INVO3
INVO2
116
120
95
149
49
96
147
48
36
37
94
97
150
148
CP2
FELD
HDN
FELD
FVD
#VCLR
FHD
HCLR
DSPBLK
DSPSYNC
FBLK
FSYNC
#VDN
HDN
CSYNC
BF
SCR
YOUT0
I
YOUT9
CCDCK
CLKO
GLSYNC
BSD
GLBSC
SCMP
FVRP
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CK2
CK1
CSYNC
FELD
1
32
26
7
TDI
TDO
TCK
TMS
43
113
115
135-144
2,3,5,6
8,10-14
123-132
40
37
20-23,25,27
28,30,31,33
NTSC/PAL
18
INT
HDN
CLK
LPF
EX28M
SYNC
SEP
42
44
DA0-DA9
14-23
4-13
G1
I
G10
R1
I
R10
CLKG
CLKR
62
98
89
67
66
58
70
71
69
73
74
106
102
79
80
103
83
65
38
ROUT
GOUT
1
7
3
5
BURST
SEP
U11
2
1
LPF
BUFFER
LPF
FL2
AMP
OPY OUT
SCB
#VDTRG
SCFINE
RESET
OPC OUT
SC OUT
SY OUT
VIDEO
AMP
BUFFER
BUFFER
MIX/AMP
MIX/AMP
BUFFER
CHARA
CSYNC
BUFFER
AMP
EX28M
46
43
EX28M OUT
SCB OUT
VDTRG IN
INT IN
-5V
SCFINE IN
-5V
RESET IN
GL IN
+3V
+3V
OPC OUT
+3V
+3VD
VBS OUT
+3VD
+3VD
VIDEO OUT
+0.5V
+0.5V
OPY OUT
+0.5V
+5V
SC OUT
+5V
+5V
SY OUT
+6.7V
+6.7V
+6.7V
D0 IN
D1 IN
D2 IN
D3 IN
D4 IN
D5 IN
D6 IN
D7 IN
A0 IN
A1 IN
A2 IN
A3 IN
A4 IN
A5 IN
A6 IN
A7 IN
WE IN
CS5 IN
RE IN
TMS
TCK
TDI
TDO
FERR
5
10
11
13
14
15
16
18
19
20
22
23
24
26
27
28
30
31
32
34
35
36
38
39
40
42
43
44
46
48
49
51
53
55
57
59
61
63
50
52
54
56
58
60
62
64
65
66
67
71
72
73
74
76
INT
-5V
+3V
+3VD
+0.5V
+5V
+6.7V
FVR
SPCO
SLPF
HPCO
HLPF2
HLPF1
COIN
CXIN
VC1
VCXO
VCO
SCIN
FSC4
#VDTRG
SCB
RESET
1
1
5
2
#GL IN
4
2
2
4
(PAL ONLY)
1
1
6
2
4
2
Q
3
6
5
3
SCFINE
5
2
1
Q
D
CK
CLR
''H''
''H''
LPF
INT
4
2
68
87
61
50
101
111
64
4
2
VD2
SCB
CLR
TCLR
POR
WEN
CSIN
REN
DATA0
I
DATA7
ADRS0
I
ADRS7
+3VD
(PAL)
(NTSC)
156
176
155
118
117
92
157-164
D0-D7
168-175
A0-A7
WHD
PWHD
NP
NTSC/PAL
+5V
ENCODER  BOARD
BLOCK  DIAGRAM  OF  ENCODER  BOARD
U1(a)
U2
A/D CONVERTER
U1(b)
Q47,Q49
U22(c)
R188
P1
Q48
U4(a)
U5
A/D CONVERTER
Q50,Q52
U22(b)
R190
U6(a)
U7
A/D CONVERTER
U6(b)
Q44,Q46
U22(a)
U3
R132
TO
DSP
BOARD
...P8
Q45
U24
U23
U8
GATE ARRAY
LOGIC
U25
U20
D/A CONVERTER
U12(a)
U12(c)
U15(b)
Q38
U19
X3
Q42
Q53
R140
INT 8FSC
Q39
Q40
U18
D8
D9
X1
Q10,Q11,Q20-Q24,Q36
U13
GEN-LOCK
U9
Q2-Q5
Q43
U14
U16
Q7-Q9
Q19
Q17,Q18
Q6
Q25,Q26
Q27
Q28,Q29
Q30-Q34
Q37
Q12-Q16
Q35
U17
U15(a)
D3
R192
D4
TO
DSP
BOARD
...P7
P2
– 13 –
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