Panasonic PT-EX12KU / PT-EX12KE (serv.man3) Service Manual ▷ View online
-89-
Electrical Adjustment
Grp / No. Item
Function
Range
Initial
Note
24 YE_FX_VAL
PC-Rear
0 - 255
60
25 YE_FX_VAL
PC-Dynamic
0 - 255
60
26 YE_FX_VAL
AV-Standard
0 - 255
60
27 YE_FX_VAL
AV-Cinema
0 - 255
60
28 YE_FX_VAL
AV-Dynamic
0 - 255
60
29 DAC_Range Max
0 - 255
255
30 DAC_Range Min
0 - 255
32
31 P_PWM_WIDTH
0 - 16383
600
32 DAC_LEVEL
For Ye Auto
0 - 255
250
33 YE_APLUsed
APL usage
0 - 255
20
34 YE_APLOff
0 - 255
0
35 YE_FIX_VAL_SW
PC-Standard
0 - 1
1
36 YE_FIX_VAL_SW
PC-Rear
0 - 1
1
37 YE_FIX_VAL_SW
PC-Dynamic
0 - 1
1
38 YE_FIX_VAL_SW
AV-Standard
0 - 1
1
39 YE_FIX_VAL_SW
AV-Cinema
0 - 1
1
40 YE_FIX_VAL_SW
AV-Dynamic
0 - 1
1
41 YE_APL_A0
0 - 127
30
42 YE_APL_A1
0 - 127
62
43 YE_APL_A2
0 - 127
75
44 YE_APL_A3
0 - 127
90
45 YE_APL_A4
0 - 127
100
46 YE_GAIN_A0
- 256 - 256
-20
47 YE_GAIN_A1
- 256 - 256
-12
48 YE_GAIN_A2
- 256 - 256
-4
49 YE_GAIN_A3
- 256 - 256
13
50 YE_GAIN_A4
- 256 - 256
30
51 YE_APL_B0
0 - 127
8
52 YE_APL_B1
0 - 127
19
53 YE_APL_B2
0 - 127
30
54 YE_APL_B3
0 - 127
38
55 YE_APL_B4
0 - 127
45
56 YE_GAIN_B0
- 256 - 256
20
57 YE_GAIN_B1
- 256 - 256
26
58 YE_GAIN_B2
- 256 - 256
43
59 YE_GAIN_B3
- 256 - 256
70
60 YE_GAIN_B4
- 256 - 256
100
61 YE_APL_C0
0 - 127
7
62 YE_APL_C1
0 - 127
25
63 YE_APL_C2
0 - 127
40
64 YE_APL_C3
0 - 127
50
65 YE_APL_C4
0 - 127
60
66 YE_GAIN_C0
0 - 511
300
67 YE_GAIN_C1
0 - 511
278
68 YE_GAIN_C2
0 - 511
207
69 YE_GAIN_C3
0 - 511
120
70 YE_GAIN_C4
0 - 511
100
71 YEOFF_YE_SW
0 - 1
1
72 YEOFF_YE_LVL
0 - 255
255
73 COLOR_AJY_YEAUTO_PC
0 - 16383
150
128
74 COLOR_AJY_YEAUTO_AV
0 - 16383
150
128
75 COLOR_AJY_YEOFF_PC
0 - 16383
150
128
76 COLOR_AJY_YEOFF_AV
0 - 16383
150
128
77 YE_Calc_Mode
0 - 1
0
78 DAT_YEBG_OFFOT
0: On, 1: Off
0 - 1
0
83
FINE FPGA Sharpnes
0 Sharpness MIN [PC-SD]
0 - 127
0
1 Sharpness MIN [PC-HD]
0 - 127
0
2 Sharpness MIN [AV-SD]
0 - 127
0
3 Sharpness MIN [AV-HD]
0 - 127
0
4 Sharpness CENTER [PC-SD]
0 - 127
35
5 Sharpness CENTER [PC-HD]
0 - 127
30
6 Sharpness CENTER [AV-SD]
0 - 127
46
7 Sharpness CENTER [AV-HD]
0 - 127
55
8 Sharpness MAX [PC-SD]
0 - 127
100
9 Sharpness MAX [PC-HD]
0 - 127
100
10 Sharpness MAX [AV-SD]
0 - 127
77
11 Sharpness MAX [AV-HD]
0 - 127
100
84
FINE FPGA - Blending
-90-
Electrical Adjustment
Grp / No. Item
Function
Range
Initial
Note
0 BKMOD
0: Blending Mode (NORMAL) Layered Disable
1: Blending Mode (BLANKINK)Layered Disable
2: Blending Mode (NORMAL)Layered Enable
3: Blending Mode (BLANKING)Layered Enable
0 - 3
3
1 BLD_I_SIZE_H
Inner Frame Width H
0 - 255
3
2 BLD_I_SIZE_V
Inner Frame Width V
0 - 255
3
3 BLD_CURVE
Curve
0 - 255
0
4 RGB_GAIN
PC-Standard
0 - 511
256
5 RGB_GAIN
PC-Real
0 - 511
256
6 RGB_GAIN
PC-Dynamic
0 - 511
256
7 RGB_GAIN
AV-Standard
0 - 511
256
8 RGB_GAIN
AV-Cinema
0 - 511
256
9 RGB_GAIN
AV-Dynamic
0 - 511
256
10 Bld_Exp_Int
PC-Standard
0 -255
118
11 Bld_Exp_Int
PC-Real
0 -255
118
12 Bld_Exp_Int
PC-Dynamic
0 -255
118
13 Bld_Exp_Int
AV-Standard
0 -255
118
14 Bld_Exp_Int
AV-Cinema
0 -255
118
15 Bld_Exp_Int
AV-Dynamic
0 -255
118
16 Bld_off_mult
PC-Standard
0 -255
64
17 Bld_off_mult
PC-Real
0 -255
64
18 Bld_off_mult
PC-Dynamic
0 -255
64
19 Bld_off_mult
AV-Standard
0 -255
64
20 Bld_off_mult
AV-Cinema
0 -255
64
21 Bld_off_mult
AV-Dynamic
0 -255
64
22 Bld_N_DT_NO
Blending: tabale type
0 - 15
15
23 MultImgColor
0 - 47
15
85
AV FPGA Dot Clock Rate
1 PC-Dot Clock Rate
Slot-DIgtal
1002
2 AV-Dot Clock Rate
Slot-DIgital
1002
86
MOTHER FPGA DLYCNT
0 DLYCNT (SLOT1)
SLOT1 Clock Phase [DVI-Dsub]
0 - 255
7
1 DLYCNT (SLOT1)
SLOT1 Clock Phase [HDCP-DVI]
0 - 255
7
2 DLYCNT (SLOT1)
SLOT1 Clock Phase [Dual Fanc-SDI]
0 - 255
3
3 DLYCNT (SLOT1)
SLOT1 Clock Phase [Dual Link-SDI]
0 - 255
3
4 DLYCNT (SLOT1)
SLOT1 Clock Phase [AMIMON]
0 - 255
3
5 DLYCNT (SLOT1)
SLOT1 Clock Phase [Reserved]
0 - 255
1
6 DLYCNT (SLOT1)
SLOT1 Clock Phase [Reserved]
0 - 255
1
7 DLYCNT (SLOT1)
SLOT1 Clock Phase [Reserved]
0 - 255
1
8 DLYCNT (SLOT1)
SLOT1 Clock Phase [Reserved]
0 - 255
1
9 DLYCNT (SLOT1)
SLOT1 Clock Phase [Reserved]
0 - 255
1
10 DLYCNT (SLOT2)
SLOT2 Clock Phase [DVI-Dsub]
0 - 255
7
11 DLYCNT (SLOT2)
SLOT2 Clock Phase [HDCP-DVI]
0 - 255
7
12 DLYCNT (SLOT2)
SLOT2 Clock Phase [Dual Fanc-SDI]
0 - 255
3
13 DLYCNT (SLOT2)
SLOT2 Clock Phase [Dual Link-SDI]
0 - 255
3
14 DLYCNT (SLOT2)
SLOT2 Clock Phase [AMIMON]
0 - 255
3
15 DLYCNT (SLOT2)
SLOT2 Clock Phase [Reserved]
0 - 255
1
16 DLYCNT (SLOT2)
SLOT2 Clock Phase [Reserved]
0 - 255
1
17 DLYCNT (SLOT2)
SLOT2 Clock Phase [Reserved]
0 - 255
1
18 DLYCNT (SLOT2)
SLOT2 Clock Phase [Reserved]
0 - 255
1
19 DLYCNT (SLOT2)
SLOT2 Clock Phase [Reserved]
0 - 255
1
88
FINE FPGA-Blending offset
0 BLD_4OffSETMD
0 - 3
0
1 BLD_LT_OFFSETR
-32768-32767
0
2 BLD_LT_OFFSETG
-32768-32767
0
3 BLD_LT_OFFSETB
-32768-32767
0
4 BLD_RT_OFFSETR
-32768-32767
0
5 BLD_RT_OFFSETG
-32768-32767
0
6 BLD_RT_OFFSETB
-32768-32767
0
7 BLD_UP_OFFSETR
-32768-32767
0
8 BLD_UP_OFFSETG
-32768-32767
0
9 BLD_UP_OFFSETB
-32768-32767
0
10 BLD_DN_OFFSETR
-32768-32767
0
11 BLD_DN_OFFSETG
-32768-32767
0
12 BLD_DN_OFFSETB
-32768-32767
0
90
SW FPGA -SETTING
0 LVDS_AJY_TIM
AV
0 - 7
0
1 LVDS_SJY_PHASE
AV
0 - 255
126
2 RSTOFF
AV
0 - 1
0
3 LVDS_AJY_TIM
Slot
0 - 7
0
-91-
Electrical Adjustment
Grp / No. Item
Function
Range
Initial
Note
4 LVDS_AJY_PHASE
Slot
0 - 255
135
5 RSTOFF
Slot
0 - 1
0
100
CXA7009
0 G SIG Center
0 - 63
37
1 B SIG Center
0 - 63
37
2 R SIG Center
0 - 255
37
3 G Gain Control
0 - 255
194
4 B Gain Control
0 - 255
194
5 R Gain Control
0 - 255
194
6 G Bright Control
0 - 255
0
7 B Bright Control
0 - 255
0
8 R Bright Control
0 - 255
0
9 G VCOM Control
0 - 127
100
10 B VCOM Control
0 - 127
100
11 R VCOM Control
0 - 127
100
12 G SID Control A
0 - 255
16
13 B SID Control A
0 - 255
16
14 R SID Control A
0 - 255
16
15 G SID Control B
0 - 255
150
16 B SID Control B
0 - 255
150
17 R SID Control B
0 - 255
150
18 G FRINV
0 - 1
1
19 B FRINV
0 - 1
0
20 R FRINV
0 - 1
0
101
CXD3548_TG
0 SCANM
0 - 3
2
1 FRPM
0 - 3
2
2 SCAN_SEL
0 - 1
1
3 HP
0 - 2047
14
4 VP_G
0 - 255
15
5 SHP_R
0 - 127
45
6 SHP_G
0 - 127
45
7 SHP_B
0 - 127
45
8 FRP_HP
0 - 2047
91
9 PRG_U
0 - 1023
49
10 PRG_D
0 - 1023
115
11 HST_R_PF
0 - 127
22
12 HST_R_PC
0 - 127
7
13 DCK1_R_WA
0 - 127
139
14 DCK1_R_F
0 - 127
48
15 DCK2_R_WA
0 - 127
0
16 DCK2_R_F
0 - 127
0
17 DCK3_R_WA
0 - 127
139
18 DCK3_R_F
0 - 127
0
19 DCK4_R_WA
0 - 127
0
20 DCK4_R_F
0 - 127
0
21 HST_G_PF
0 - 127
22
22 HST_G_PC
0 - 127
7
23 DCK1_G_WA
0 - 127
139
24 DCK1_G_F
0 - 127
48
25 DCK2_G_WA
0 - 127
0
26 DCK2_G_F
0 - 127
0
27 DCK3_G_WA
0 - 127
139
28 DCK3_G_F
0 - 127
0
29 DCK4_G_WA
0 - 127
0
30 DCK4_G_F
0 - 127
0
31 HST_B_PF
0 - 127
22
32 HST_B_PC
0 - 127
7
33 DCK1_B_WA
0 - 127
139
34 DCK1_B_F
0 - 127
48
35 DCK2_B_WA
0 - 127
0
36 DCK2_B_F
0 - 127
0
37 DCK3_B_WA
0 - 127
139
38 DCK3_B_F
0 - 127
0
39 DCK4_B_WA
0 - 127
0
40 DCK4_B_F
0 - 127
0
41 PCG_U
0 - 1023
49
42 PCG_D
0 - 1023
213
43 ENB_U
0 - 1023
124
44 ENB_D
0 - 1023
24
45 CLR_U
0 - 1023
0
-92-
Electrical Adjustment
Grp / No. Item
Function
Range
Initial
Note
46 CLR_D
0 - 1023
0
47 VCKP
0 - 2047
49
48 VCKPD
0 - 2047
1344
49 VSTP
0 - 255
125
50 DFT_ON
0 - 1
0
51 HPC_R_DAT0
0 - 8191
0
52 HPC_R_DAT1
0 - 8191
0
53 HPC_G_DAT0
0 - 8191
0
54 HPC_G_DAT1
0 - 8191
0
55 HPC_B_DAT0
0 - 8191
0
56 HPC_B_DAT1
0 - 8191
0
57 SCAN_HP
0 - 2047
91
102
CXD3548_DSP_PRE
0 USR_R_GAIN
0 - 1023
512
1 USR_G_GAIN
0 - 1023
512
2 USR_B_GAIN
0 - 1023
512
3 USR_R_BRIGHT
0 - 8191
0
4 USR_G_BRIGHT
0 - 8191
0
5 USR_B_BRIGHT
0 - 8191
0
6 FRM_DAT
0 - 255
0
7 SEL_MODE
0 - 7
0
8 RLR_DUM_PIX
0 -127
4
103
CXD3548_GAM
0 GAM_ON
0 - 1
1
1 USR_R_GAIN
0 - 1023
512
2 USR_G_GAIN
0 - 1023
512
3 USR_B_GAIN
0 - 1023
512
4 USR_R_BRIGHT
0 - 8191
0
5 USR_G_BRIGHT
0 - 8191
0
6 USR_B_BRIGHT
0 - 8191
0
104
CXD3550_USC1
0 USC1_GAIN_R
0 - 1023
512
1 USC1_GAIN_G
0 - 1023
512
2 USC1_GAIN_B
0 - 1023
512
3 USC1_BRIGHT_R
0 - 8191
0
4 USC1_BRIGHT_G
0 - 8191
0
5 USC1_BRIGHT_B
0 - 8191
0
6 USC2_GAIN_R
0 - 1023
512
7 USC2_GAIN_G
0 - 1023
512
8 USC2_GAIN_B
0 - 1023
512
9 USC2_BRIGHT_R
0 - 8191
0
10 USC2_BRIGHT_G
0 - 8191
0
11 USC2_BRIGHT_B
0 - 8191
0
104
CXD3548_VXT
0 VXT_DETECT_ON
0 - 1
1
1 VXT_GSEL
0 - 3
2
2 VXT_RCALC
0 - 1
0
3 VXT_GCALC
0 - 1
0
4 VXT_BCALC
0 - 1
0
5 VXT_ON
0 - 1
1
6 VXT_RDATU1
0 - 255
8
7 VXT_RDATU2
0 - 255
9
8 VXT_RDATU3
0 - 255
22
9 VXT_GDATU1
0 - 255
8
10 VXT_GDATU2
0 - 255
9
11 VXT_GDATU3
0 - 255
22
12 VXT_BDATU1
0 - 255
8
13 VXT_BDATU2
0 - 255
9
14 VXT_BDATU3
0 - 255
22
15 VXT_RDATL1
0 - 255
4
16 VXT_RDATL2
0 - 255
5
17 VXT_RDATL3
0 - 255
11
18 VXT_GDATL1
0 - 255
4
19 VXT_GDATL2
0 - 255
5
20 VXT_GDATL3
0 - 255
11
21 VXT_BDATL1
0 - 255
4
22 VXT_BDATL2
0 - 255
5
23 VXT_BDATL3
0 - 255
11
24 VXT_TH_ON
0 - 255
15
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