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5

JUL 2002

Edition 1.0

DP-1510P/1810P

     

/1810F/2010E

The System Control Block consists of the following IC that control the general functions.

SDRAM 8MB

SDRAM 8MB

CPU SH2

(IC1)

MSC

DZAC000166

(IC5)

F-ROM 4MB

Program

(IC10)

F-ROM 2MB

(DP-1810F only)

(DP-1810F only)

(DP-2010E only)

Image

(IC19)

MODEM

MN195006

(IC20)

MN86076

(IC51)

Analog

FrontEnd

DRAM 2MB

(IC7)

I-NET Option

Connector

CNP123)

PRI I/F

HIF

IC76)

F-ROM CARD

(Boot)

Connector

(CNP104)

API

(IC14)

VHCT

244

BRIDGE

DZAC000233

(IC34)

CODEC

PM-22c

(IC33)

Sort Memory

SDRAM 8MB

A-BUS 3V

D-BUS 3V

MA-BUS 3V

AL-BUS 5V

IOD-BUS 5V

PanelCPU

Scanning

Mechanism

Control CPU

244

2/4/8MB

DANCE

DZAC000234

(IC28)

OD

Page Memory

SDRAM 8MB

ID

BMD

BMA

BID(15-0)

PMD

PMA

PWM

LSU

LPC3

PNL

SCN

S-DRAM

Option

Connector

(CNP113)

6

DP-1510P/1810P

     

/1810F/2010E

JUL 2002

Edition 1.0

The System CPU (SH7041) is a 32-bit RISC (Reduced Instruction Set Computer) type of CPU and
DMA Control, Serial Communication Port, Timer Control, Interrupt Control, DRAM Control, and I/O Port
are integrated into 1 chip. Mask ROM (64k byte) is already installed and it controls the Monitor, High
Speed managing Task and Boot Programming.

• Serial Communication Port

It has a 2ch Serial Communication Port and is used to interface the following devices.
CPU 

←→

 Panel Unit (Panel CPU)

CPU 

←→

 Sub CPU for scanning (M16C/162)

• Timer Control

It is used to program the standard timer.

• Interrupt Control

It controls receipt & transfer to CPU the interrupt from MSC, Option, etc.

• DRAM Control

It generates DRAM Control Signal and Refresh Control when the power is ON.

• I/O Port

It is used to control lines and reset control around LSI.

DZAC000166 (MSC) is a System Control Gate Array and provides the CPU peripheral function.

• DMA Control

It has a 4ch DMA Control and is used to transfer data between the following devices.
Printer Interface 

←→

 Image Data Memory (DRAM)

• Interrupt Control

It controls receipt & transfer to CPU the interrupt from CODEC and LSI, etc.

• DRAM Control

It selects DRAM Control Signal and generates Control Signal when transferring DMA.

• BUS Control

Data control between System BUS (+3.3V) and I/O BUS (+5V)

• Address Decoder Control

It generates Chip select signal of peripheral LSI.

This system consists of the following memory.

• F-ROM (IC10) 

→

 F-ROM (4MB) for programming

The program is booted from F-ROM Card or Parallel Port Interface.

• DRAM (IC7) 

→

• F-ROM (IC19) 

→

 F-ROM (2MB) for image (DP-1810F only).

7

JUL 2002

Edition 1.0

DP-1510P/1810P

     

/1810F/2010E

The Image Data Circuit is independent of System circuit from Page Memory / Sort Memory circuit due to
high speed scanning and printing. As a result of this, all image data is managed by the Image Data circuit
and only coded data is transferred to the System Data BUS.

S-DRAM 8MB

(DP-2010E only)

(IC11)

MN86076

(IC51)

(IC54,55)

PDL OPTION

DANCE

DZAC000234

(IC28)

PWM

(IC26)

BRIDGE

DZAC000233

(IC34)

S-DRAM 8MB

(IC30)

S-DRAM 8MB

(IC31)

S-DRAM 8MB

(IC35)

S-DRAM

 OPTION

CCD (207)

LSU (1124)

LPC3 (19129)

+5V System BUS

+3V System BUS

244

CODEC

PM-22c

(IC33)

BID-BUS 3V

LD-BUS 3V

CN113

CN121

CN121

5    3V

Analog

F

ront End

Pr

inter Mechanism Control CPU

Connector

Connector

8

DP-1510P/1810P

     

/1810F/2010E

JUL 2002

Edition 1.0

DZAC000234 (DANCE) is a Document Adaptor for New Copier Engine (Gate Array) and provides the
Image Control peripheral function and Recording Data Control.

• DMA Control

It is used to transfer data between the following devices.

• Rotation Management

The rotation is carried out by the hardware when transferring the route.

• S-DRAM Control

It generates S-DRAM Control Signal for Page memory and Refresh Control when the power is ON. It
does not backup the Page Memory.

• PDL Data Transfer

When installing the PDL Option, the actual coded data is retrieved on the PDL side first and is
transferred to Page Memory (S-DRAM). Then, the coded data is transferred to the PDL Option on the
System side.

• Binary Gray Scale Conversion

The signal of a binary-level image such as copying is converted into a multiple-value (256-scale)
image signal. The signal is transferred to an external PWM control LSI for multiple-value recording.
A maximum of 7-by-7 pixels around an area is referred to in layers for conversion into multiple-value
signal.

• Gray-Level Enhancement

This control function allows expressing higher-level scales than using a recorded signal, by reducing
line density into 1/2 or 1/3 on the original after binary-to-multiple value conversion. This capability
increases reproduction of gray scale images such as photographs.

• Laser Pulse Width Control

After smoothing, the IPC controls Laser pulse width by the software setting of the print quality.

• Image Range Isolation Circuit

It identifies the halftone picture range and controls smoothing, Binary Gray Scale Conversion, and
Laser pulse width control to eliminate blotching of the recording picture which has undergone error
diffusion or other process.

Scanning Control LSI (MN86076)

→

Page Memory (S-DRAM)

:

Scanning Route

Page Memory (S-DRAM)

→

Sort Memory Control Gate Array
(BRIDGE)

:

Coding Route

Sort Memory Control Gate Array
(BRIDGE)

→

Page Memory (S-DRAM)

:

Decoding Route

Page Memory (S-DRAM)

→

PMW Control LSI (LP)

:

Recording Route

System Memory (DRAM)

→

Page Memory

:

Report Route

Page Memory (S-DRAM)

→

CODEC for Image (PM-22c) :

Rotation (Send)

Page Memory (S-DRAM)

→

PMW Control LSI (LP)

:

Copy, Rotation (Receive)