Panasonic KX-TDA6110XJ / KX-TDA6110X Service Manual ▷ View online
8 IC DATA
8.1. FPGA (IC614)
Pin No.
Pin Name
I/O
DiscriptionPin Usage
1
nCSCL3
O
chip select signal for CircLink#3 on BUS-ME card
2
S3_NETREF
I
Network reference clock from Expansion shelf #3
3
+3.3V(I/OVoltage)
Power Supply for Output Buffer Drivers(per bank)
4
nDIAG3
O
Diagnosis function contorl signal for CircLink#3
5
nINTRCL3
I
Interupt singnal from CircLink#3 on BUS-ME card
6
BS32
I
Expansion shelf #3 BUS-S card Status signal2
7
BS31
I
Expansion shelf #3 BUS-S card Status signal1
8
nLOS3
I
Loss of sync signal from Expansion shelf #3
9
Groud
Ground
10
nDETCL2
I
BUS-ME Card #2 detection
11
nCMI2B
O
Circlnk#2 CMI Modem control signal
12
nSRST2
O
Expansion shelf #2 Reset signal
13
SSSTAT2
I
Expansion shelf #2 BUS cable detection port
14
nCSCL2
O
chip select signal for CircLink #2 on BUS-ME card
25
KX-TDA6110XJ / KX-TDA6110X
Pin No.
Pin Name
I/O
DiscriptionPin Usage
15
S2_NETREF
I
Network reference clock from Expansion shelf #2
16
Groud
Ground
17
nDIAG2
O
Diagnosis function contorl signal for CircLink #2 on BUS-ME Card
18
nINTRCL2
I
Interupt singnal from CircLink #2
19
+3.3V(I/OVoltage)
Power Supply for Output Buffer Drivers(per bank)
20
BS22
I
Expansion shelf #2 BUS-S card Status signal2
21
BS21
I
Expansion shelf #2 BUS-S card Status signal1
22
Groud
Ground
23
nLOS2
I
Loss of sync signal from Expansion shelf #2
24
nCMI1B
O
Circlnk#1 CMI Modem control signal
25
nSRST1
O
Expansion shelf #1 Reset signal
26
SSSTAT1
I
Expansion shelf #1 BUS cable detection port
27
nCSCL1
O
chip select signal for CircLink #1 on BUS-ME card
28
S1_NETREF
I
Network reference clock from Expansion shelf #1
29
Groud
Ground
30
nDIAG1
O
Diagnosis function contorl signal for CircLink #1
31
nINTRCL1
I
Interupt singnal from CircLink #1
32
BS12
I
Expansion shelf #1 BUS-S card Status signal2
33
BS11
I
Expansion shelf #1 BUS-S card Status signal1
34
+3.3V(I/OVoltage)
Power Supply for Output Buffer Drivers(per bank)
35
nLOS1
I
Loss of sync signal from Expansion shelf #1
36
nWRZL
O
nWrite/Read signal for CTSW
37
M1
Configuration Mode Selection
38
M0
Configuration Mode Selection
39
M2
Configuration Mode Selection
40
(NC)
UNUSED
41
(NC)
UNUSED
42
Groud
Ground
43
+3.3V(I/OVoltage)
Power Supply for Output Buffer Drivers(per bank)
44
nDTAZL
I
Data acknowledge signal for CTSW
45
Groud
Ground
46
nDSZL
O
Data strobe signal for CTSW
47
nCSZL
O
Chip select signal for CTSW
48
+2.5V(AUX Voltage)
Power Supply for Auxiliary Circuits
49
+1.2V(CoreVoltage)
Power Supply for Internal Core Logic
50
(NC)
UNUSED
51
(NC)
UNUSED
52
(NC)
UNUSED
53
C16M
I
Global Clock Buffer Input(16MHz)
54
+3.3V(I/OVoltage)
Power Supply for Output Buffer Drivers(per bank)
55
(NC)
UNUSED
56
(NC)
UNUSED
57
(NC)
UNUSED
58
(NC)
UNUSED
59
(NC)
UNUSED
60
nCSTK
O
not use this signal
61
+1.2V(CoreVoltage)
Power Supply for Internal Core Logic
62
+2.5V(AUX Voltage)
Power Supply for Auxiliary Circuits
63
(NC)
UNUSED
64
Groud
Ground
65
(NC)
UNUSED
66
+3.3V(I/OVoltage)
Power Supply for Output Buffer Drivers(per bank)
67
Groud
Ground
68
(NC)
UNUSED
69
ODEZL
O
Output port enable signal for CTSW
70
MnWRD
I
nWrite/Read signal from EMPR Card
71
DONE
"Configuration Done
72
CCLK
Configuration Clock
73
MnWE0
I
Write enable low byte signal from EMPR Card
74
MnWE1
I
Write enable low byte signal from EMPR Card
75
+3.3V(I/OVoltage)
Power Supply for Output Buffer Drivers(per bank)
76
MnRD
I
Read signal from EMPR Card
77
(NC)
UNUSED
78
MnRDY
O
Ready signal to EMPR Card
79
MnCS
I
Chip select signal from EMPR Card
80
MnIRQ
O
Interupt signal to EMPR Card
81
Groud
Ground
26
KX-TDA6110XJ / KX-TDA6110X
Pin No.
Pin Name
I/O
DiscriptionPin Usage
82
LA[0]
UNUSED (Rserved)
83
LA[1]
I
Address bus(EMPR local bus)[1]
84
LA[2]
I
Address bus(EMPR local bus)[2]
85
LA[3]
I
Address bus(EMPR local bus)[3]
86
LA[4]
I
Address bus(EMPR local bus)[4]
87
LA[5]
I
Address bus(EMPR local bus)[5]
88
Groud
Ground
89
CT_NETREF
3sO
90
nRDCL
O
Read signal for CircLink #1
91
+3.3V(I/OVoltage)
Power Supply for Output Buffer Drivers(per bank)
92
nWECL
O
Write signal for CircLink #1
93
nRST
I
Syetem reset input port from EMPR Card
94
Groud
Ground
95
LA[22]
UNUSED (Rserved)
96
LA[23]
I
Address bus(EMPR local bus)[23]
97
LA[24]
I
Address bus(EMPR local bus)[24]
98
LA[25]
I
Address bus(EMPR local bus)[25]
99
LD[0]
I/O
Data bus(EMPR local data bus)[0]LSB
100
LD[1]
I/O
Data bus(EMPR local data bus)[1]
101
Groud
Ground
102
LD[2]
I/O
Data bus(EMPR local data bus)[2]
103
LD[3]
I/O
Data bus(EMPR local data bus)[3]
104
LD[4]
I/O
Data bus(EMPR local data bus)[4]
105
LD[5]
I/O
Data bus(EMPR local data bus)[5]
106
+3.3V(I/OVoltage)
Power Supply for Output Buffer Drivers(per bank)
107
LD[6]
I/O
Data bus(EMPR local data bus)[6]
108
LD[7]
3s.O
Data bus(EMPR local data bus)[7]MSB
109
TDO
JTAG Test Data output
110
TCK
JTAG Test Clock
111
TMS
JTAG Test Mode Select
112
CRDID0
I
Card ID port[0]
113
CRDID1
I
Card ID port[1]
114
Groud
Ground
115
+3.3V(I/OVoltage)
Power Supply for Output Buffer Drivers(per bank)
116
CRDID2
I
Card ID port[2]
117
Groud
Ground
118
CRDID3
I
Card ID port[3]
119
CRDID4
I
Card ID port[4]
120
+2.5V(AUX Voltage)
Power Supply for Auxiliary Circuits
121
+1.2V(CoreVoltage)
Power Supply for Internal Core Logic
122
CRDID5
I
Card ID port[5]
123
CRDID6
I
Card ID port[6]
124
CRDID7
I
Card ID port[7]
125
(NC)
UNUSED
126
+3.3V(I/OVoltage)
Power Supply for Output Buffer Drivers(per bank)
127
LED_RED
O
Status LED control port(RED)
128
LED_GREEN
O
Status LED control port(GREEN)
129
ES1S_LED
O
LINK LED #1 control port
130
ES2S_LED
O
LINK LED #2 control port
131
ES3S_LED
O
LINK LED #3 control port
132
LOCAL_nRST
UNUSED (Rserved)
133
+1.2V(CoreVoltage)
Power Supply for Internal Core Logic
134
+2.5V(AUX Voltage)
Power Supply for Auxiliary Circuits
135
nDETCL3
I
BUS-ME Card #3 detection
136
Groud
Ground
137
nCMI3B
O
Circlnk#3 CMI Modem control signal
138
+3.3V(I/OVoltage)
Power Supply for Output Buffer Drivers(per bank)
139
Groud
Ground
140
nSRST3
O
Expansion shelf #3 Reset signal
141
SSTAT3
I
Expansion shelf #3 BUS cable detect port
142
HSWAP_EN
Disable Weak Pull-up Resistors During Configuration
143
PROG_B
Program/Configure Device
144
TDI
I
JTAG Test Data Input
Note
3s.O: 3State Output
27
KX-TDA6110XJ / KX-TDA6110X
8.2. PROM (IC210)
Pin No.
Pinl Name
I/O
DiscriptionPin Usage
1
D0
O
D0 is the DATA output pin to provide data for configuring an FPGA in serial mode.
2
DNC
Do not connect.
3
CLK
I
Configuration Clock Input.
4
TDI
I
JTAG Serial Data Input.
5
TMS
I
JTAG Mode Select Input.
6
TCK
I
JTAG Clock Input.
7
nCF
O
Configuration Pulse(Open-Drain Output).
8
OE/nRESET
O
Output Enable/Reset(Open-Drain I/O).
9
DNC
Do not connect.
10
nCE
I
Chip Enable Input.
11
GND
Ground
12
DNC
Do not connect.
13
nCEO
O
(not use port) Chip Enable Output.
14
DNC
Do not connect.
15
DNC
Do not connect.
16
DNC
Do not connect.
17
TDO
O
JTAG Serial Data Output.
18
VCCINT
+3.3V Supply.
19
VCCO
+2.5V I/O Supply.
20
VCCJ
+2.5V JTAG I/O Supply.
28
KX-TDA6110XJ / KX-TDA6110X
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