Panasonic KX-TDA0470XJ / KX-TDA0470X Service Manual ▷ View online
8.3. ASIC BLOCK
Configuration :
ASIC (IC202), Reset IC (IC201), Source clock 16.384MHz (X200), etc.
Function :
ASIC (IC202)
Being connected with the backboard by 90pin connector (CN200), this provides the EC bus interface function and H.100
communication function.
(1) EC bus interface (Dual port RAM (DPRAM) communication) function
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Being connected with the backboard by 90pin connector (CN200), this provides the EC bus interface function and H.100
communication function.
(1) EC bus interface (Dual port RAM (DPRAM) communication) function
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• This is connected with the synchronized 16-bit bus that is called EC bus, for the communications with the MAIN PBX
processor.
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• All EC-bus signals from mainboard are terminated at ASIC (IC202).
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• Between this card and MAIN (EC bus), data is transmitted and received through the dual port RAM.
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• The schematic diagram is as follows.
Fig. DPRAM Communication schematic diagram
(2) H.100 interface function
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• CT-BUS function included in ASIC (IC202), being connected with the mainboard, conducts serial voice and data
communications. This board does not output clock.
Type of Reset
Description
PWR_RST
Power-on Reset
Reset function to be released in 50msec after turning on the power supply (3.3V) to the card by the power-on or
the on-line addition.
This reset is connected to the ASIC for a circuit control and the FLASH memory.
(To start up the FLASH before the LPR reset is released.)
Reset function to be released in 50msec after turning on the power supply (3.3V) to the card by the power-on or
the on-line addition.
This reset is connected to the ASIC for a circuit control and the FLASH memory.
(To start up the FLASH before the LPR reset is released.)
EC_nRST
System Reset of the PBX
Controlled directly by the CPU with MPR, and activated by supplying power to the system, self-resetting the CPU
or pressing the Reset SW on the MPR.
Controlled directly by the CPU with MPR, and activated by supplying power to the system, self-resetting the CPU
or pressing the Reset SW on the MPR.
L_nRST
Local Reset in the Card
Reset function to the device in the card, outputted from a port of the line ASIC.
After the reset of the line ASIC (the PWR_RST, EC_nRST above) is released, hold the Reset Hold status and
can release by a direction from the MPR.
Reset function to the device in the card, outputted from a port of the line ASIC.
After the reset of the line ASIC (the PWR_RST, EC_nRST above) is released, hold the Reset Hold status and
can release by a direction from the MPR.
EC Bus
Card Individual Command Reset
The access to the line ASIC by the EC bus access from the MPR can perform the Self Reset in the ASIC.
The ASIC reset returns the L_nRST to its initial state and makes it active.
After the command is issued, a reset in the ASIC is released in 16clk (2µsec) at the EC_CLK.
The access to the line ASIC by the EC bus access from the MPR can perform the Self Reset in the ASIC.
The ASIC reset returns the L_nRST to its initial state and makes it active.
After the command is issued, a reset in the ASIC is released in 16clk (2µsec) at the EC_CLK.
VoIP_nRST
IP Engine Reset
Reset signal to the IP engine block controlled from the PCC-LPR.
Outputted from a port of the line ASIC, held at the reset hold state after the start-up of the card and released from
the LPR after the start-up of the LPR.
Reset signal to the IP engine block controlled from the PCC-LPR.
Outputted from a port of the line ASIC, held at the reset hold state after the start-up of the card and released from
the LPR after the start-up of the LPR.
SUB_nRST
Sub Board Reset
Outputted from PORT19, I/O Port of SH4.After resetting a power-on, since it is in a reset input status in the initial
state, it is controlled from SH4 to cancel the reset of the Sub Board.(Reset Input Time: 2ms or more)
Outputted from PORT19, I/O Port of SH4.After resetting a power-on, since it is in a reset input status in the initial
state, it is controlled from SH4 to cancel the reset of the Sub Board.(Reset Input Time: 2ms or more)
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KX-TDA0470XJ / KX-TDA0470X
8.4. PBX INTERFACE BLOCK
Configuration :
DPRAM (IC300) etc.
Function :
DPRAM (IC300)
Bl-directional memory for communication between CPU (SH4) and mainboard of PBX.
Bl-directional memory for communication between CPU (SH4) and mainboard of PBX.
8.5. DSP BLOCK (SUB BOARD)
Configuration :
DSP (IC100), SDRAM (IC107), PHY (IC202), PLD (IC201), DSP system clock 10MHz (X201), Ethernet clock 50MHz (X200),
RJ45 integrated magnetics connector (CN201).
RJ45 integrated magnetics connector (CN201).
Function :
DSP (IC100 sub board)
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• Power Supply : +1.2V and +3.3V.
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• Package : 484-ball PFBGA.
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• Operating Clock : 10MHz.
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• Supported Voice Codec Standards : G.711, G.729A.
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• Echo Cancellation.
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• RTP/RTCP.
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• Fax Tones Detection and Generation.
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• DTMF Detection and Generation.
SDRAM (IC107_sub board)
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• Execution Area of DSP Firmware.
PHY (IC202_sub board)
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• Power Supply : +2.5V or +3.3V.
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• Package : 64-pin TQFP.
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• 10BASE-T/100BASE-TX IEEE 802.3u fast Ethernet transceiver.
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• Mll and RMII configurable.
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• Controls the LED of LINK and DATA.
PLD (IC201)
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• Switching Control between 10BASE and 100BASE.
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KX-TDA0470XJ / KX-TDA0470X
8.6. POWER SUPPLY BLOCK
As for the power of this card, +15V is supplied from the power unit by way of the mainboard connector (CN200). DC/DC
converter generates +3.3V, and +1.5V from a +15V power supply, and supplies it as the circuit power supply in this card.
converter generates +3.3V, and +1.5V from a +15V power supply, and supplies it as the circuit power supply in this card.
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KX-TDA0470XJ / KX-TDA0470X
9 IC DATA
9.1. IC100 (LPR) MAIN BOARD
Port
Pin
Terminals
I/O
ACT
Terminals Contents
PA
15
68
nIRQ3
I
L
Reserve (interrupt)
14
67
nIRQ2
I
L
DPRAM interrupt
13
66
nIRQ1
I
L
Interrupt for SAMSON (ASIC) (mainly DPRAM communication
interrupt for MPR)
interrupt for MPR)
12
65
nIRQ0
I
L
DC power down recovery detection inversion signal of LPR
inversion signal (L:recovery)
inversion signal (L:recovery)
11
64
PA11
O
L
UART port for request to send [RTS0] (RS232C)
10
62
PA10
I
L
UART port for clear to send [CTS0] (RS232C)
9
61
PA9
-
-
Reserve (general-purpose I/O)
8
60
nBREQ
I
L
Bus request signal (bus arbitration)
7
58
nBACK
O
L
Bus acknowledge signal (bus arbitration)
6
57
nRD
O
L
Read signal (bus control)
5
56
nLBS
O
L
Low byte strobe signal (bus control)
4
55
nWR
O
L
Write signal (bus control)
3
54
nWAIT
O
L
Wait signal (bus control)
2
53
nCS6
O
L
Chip select 6 signal (bus control)
1
52
PA1
-
-
Reserve (Chip Select 5 signal)
0
51
PA0
O
L
Reserve (Chip Select 4 signal)
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KX-TDA0470XJ / KX-TDA0470X
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