Panasonic KX-NS5170XSX / KX-NS5170X-SX Service Manual ▷ View online
5
KX-NS5170X/KX-NS5170SX
3 Specifications
4 General/Introduction
4.1.
General Description
This card, which is used in the free slot of KX-NS300/500 series system, can randomly connect four of SLT, DPT and APT. In DPT
connection, the XDP function allows SLT to be connected to each port in parallel.
connection, the XDP function allows SLT to be connected to each port in parallel.
Functional Block
Functional contents
Extension Interface
Number of Ports
4 ports
PT Interface
+40V/+15V Over current protective function, Voltage switching function Inter-
APT communications
D (Upward: 0.25kbps, Downward: 0.69kbps)
2W Ping-pong transmission system (31.25kbps)
Inter-DPT communications
2B+D (144kbps) 2W Ping-pong transmission system (512kbps)
Dch-control HDLC embeds eight channels in ASIC
Surge protective function
APT communications
D (Upward: 0.25kbps, Downward: 0.69kbps)
2W Ping-pong transmission system (31.25kbps)
Inter-DPT communications
2B+D (144kbps) 2W Ping-pong transmission system (512kbps)
Dch-control HDLC embeds eight channels in ASIC
Surge protective function
SLT Interface
-26V 26mA Feeding function
Dial-pulse signal detecting function
DTMF signal detecting function
Bell signal issuing function
MW voltage issuing function
Hook detecting function
Ring trip detecting function
2W/4W converting function
CODEC function
Dial-pulse signal detecting function
DTMF signal detecting function
Bell signal issuing function
MW voltage issuing function
Hook detecting function
Ring trip detecting function
2W/4W converting function
CODEC function
/A Iaw switching function
Test function (Loop back, Tone generation)
Programmable digital filtering function
Serial interface function
Caller ID (FSK) generater
PIO function
Surge protective function
Programmable digital filtering function
Serial interface function
Caller ID (FSK) generater
PIO function
Surge protective function
DTMF Receiver
4 lines for each port
Caller ID Generater
FSK/DTMF
4 lines for each port
4 lines for each port
Extension Caller ID
Supported standard
ITU-TV.23 (1200bps) FSK
BELL202 (1200bps) FSK
BELL202 (1200bps) FSK
On-board Ringer
20/25Hz 75Vrms
Phase control (Three-phase / Four-phase)
Phase control (Three-phase / Four-phase)
Control Block
CPU
NiosII included in DLC FPGA
DLC FPGA
Dual-port memory between CPU board and NiosII CPU
Flash ROM
1Mbyte
SRAM
256kbyte
ASIC
Digital PLL function
Local bus interface function
Time switch function, Gain controlling function, DPRAM function
Private telephone controlling interface function
Parallel IO function
Local bus interface function
Time switch function, Gain controlling function, DPRAM function
Private telephone controlling interface function
Parallel IO function
External Interface
RJ45: 4 ports
6
KX-NS5170X/KX-NS5170SX
5 Technical Descriptions
5.1.
Block Diagram
DHL
C
4
Block
Diagram
DPT
I/F
Dr
iv
er
&
Rec
ei
v
e
r
Se
rg
e
EMC
DTB
0
Pul
s
e
Tr
a
n
s
Po
w
e
r SE
L
Ov
er
lo
a
d
Pr
ot
ec
ti
on
PT
_
P
OW
0
DTA
0
PT
_
C
U
R
0
Port #3
(Sam
e
as
Port #1)
D1A
D2A
Por
t #1
D1C
D2C
DR
0
+4
0
V
+3
.3
V
VR
EF
VREF
+
TAC
KER
ASIC
DLC
FPGA
EP4
C
E
1
0
NI
OS
P4
[0
]
P5
[0
]
RX
[0
]
TXA[
0
]
TXB[
0
]
FLASH
ROM
8M
B
it
SR
AM
1M
B
it
A_
T
[1
2
:0
]
A[
1
9
:1
]
A[
1
6
:0
]
A
[12:0]
D_T
[7:0]
D[15:0]
D[7:0]
D[7:0]
nW
R
_
T
nRD_T
nW
R
nRD
nW
R
nRD
nW
R
nRD
nCS
_D
M
A
nC
S
_
D
M
A
nCS
nCS
_D
M
A
SR
AM
1M
B
it
A[
1
6
:0
]
D[7:0]
nW
R
nRD
nCS
nCS
0
nCS
I
nCS
0
nCS
1
nCS
20
nCS
21
nCS
20
nCS
21
nRE
S
E
T
0_M
nRE
S
E
T
nRE
S
E
T
0_M
nW
A
IT
nW
A
IT
nB
A
C
K
nB
R
E
Q
nB
A
C
K
nB
R
E
Q
nA
L
E
nA
L
E
XT
AL
16.384
MH
z
nIRQ1
nIRQ0
P
LLCLK
ECCL
K
P2
3
DELA
Y0
DEL
A
Y
0
CP[7:0]
CP
[7:0]
LDH
W
LUH
W
0
LUH
W
0
LDH
W
0
nC
ON
FIG
HW
C
L
K
2
_
M
HW
C
L
K
_
M
HW
F
H
2
_
M
HW
F
H
_
M
LDH
W
2_M
LUH
W
2_M
LDH
W
_
M
LUH
W
_
M
A_
M
[9
:0
]
D_M
[7:0]
nW
A
IT
_
M
nW
A
IT
D[7:0]
A
[9:0]
n
RD_
M
n
RD_
M
nW
R
_
M
nW
R
_
M
nC
S
_
M
nC
S
0
_
M
nC
S
1
_
M
nI
N
T
_
M
nI
N
T
0
_
M
n
INT
1_M
IRQ2
B
E
LL_S
Y
N
C
IRQ0
HAL
T
IRQ3
ACAL
M
nR
E
S
E
T
1
_
M
HW
C
L
K
3
_
M
H
W
_F
H3_M
TO
und
er
boar
d
TO
upp
er
boar
d
nCS
nRE
S
E
T
Har
d
Revi
si
on
CA
R
D
ID[7:0]
+
40V
+
3.3V
n
R
ES
ET
0
_
M
SH
W
_
CL
K
SH
W
_
F
H
SH
W
F
H
SH
W
C
L
K
LUH
W
0
LUH
W
0
LDH
W
LD
H
W
TM
S
TC
K
TD
I
TD
O
Debug
JT
A
G
Port
S
i3226
1
nC_CS
[0]
C_INT
[0]
40V
Se
rg
e
EM
C
DCDC
40V
DCDC
Se
rg
e
EM
C
SL
IC
/C
O
D
EC
2c
h
C_DOUT
nS
L
C
R
S
T
TA
RA
TB
RB
LD
H
W
LU
H
W
1
HW
F
H
HW
C
L
K
C_DIN
C_DC
LK
SPI
0
PCM
H
W
SLT
I/F
SLT
I/F
+1
5
V
DHLC
DPT
I/F
Dr
iv
er
&
Rec
ei
v
e
r
Se
rg
e
EMC
DTB
1
Pul
s
e
Tr
a
n
s
Po
w
e
r SE
L
Ov
er
lo
a
d
Pr
ot
ec
ti
on
PT
_
P
OW
1
DTA
1
PT
_
C
U
R
1
D1B
D2B
DR
1
+4
0
V
+1
5
V
Por
t #2
DHLC
TC
RC
Port #4
(Sam
e
as
Port #
2
)
D1D
D2D
TD
RD
PT
C
T
R
PT
CTR
nC_CS
[1:0]
C_
DOUT
C_DIN
C_
DC
L
K
nS
L
C
R
S
T
(I
/O
)
C_INT
[0]
VREF
-
VREF
C
Ov
e
r
Vo
lt
age
Pro
te
ct
io
n
DC/
DC
+1
5
V
POR
T1
-2
POR
T3
-4
XT
AL
25M
H
z
CAR
D
ID
CLK
CA
R
D
ID[3:0](
I/
O)
Se
ri
a
l
RO
M
for Confi
g
4M
bi
t
DAT
A
DCLK
nC
S
O
DAT
A
DCLK
nCS
ASDO
ASDI
C_INT
[1]
IRQ6
IRQ7
nW
R
_
L
nRD_L
D_L[15:0]
A_
L
[1
9
:0
]
DC/
DC
+2
.5
V
+1
.2
V
P2
4
SH
W
C
L
K
SH
W
F
H
HW
C
L
K
HW
F
H
LUH
W
1
LUH
W
1
+5
V
DC/
DC
A
_L[19:1]
A
_L[16:0]
A
_
L[16:0]
D_L[15:0]
D_L[7:0]
D_L[7:0]
nW
R
_
L
nW
R
_
L
nW
R
_
L
nRD_L
nRD_L
nRD_L
nW
R
_
L
nRD_L
A_
L
[1
9
:0
]
D_L[15:0]
HW
F
H
HW
C
L
K
0
HW
F
H
HW
C
L
K
KX-NS5170X/SX BLOCK DIAGRAM
7
KX-NS5170X/KX-NS5170SX
5.2.
Hardware Functional Specification
5.2.1.
Control-System Circuit
5.2.1.1.
DLC FPGA
5.2.1.2.
TACKER ASIC
• Local TSW
Exchanges the time slots between CT bus (1024ch) and local highway (64ch).
Function
Specifications
FPGA Internal Processer
NiosII CPU
Interface
CPU Board I/F
Bus Timing
TI CortexA8 CPU Bus Interface
Data Bus
8bit
Address Bus
11bit
Interrupt Control
External Interrupt
Up to 2
Internal Interrupt
Up to 3
SLIC Control
Number of SLIC
Up to 2
DPT Control
Delay Measurement
16bit with data latch
SLC
MPR_BUS
DLC_FPGA
DLC_FPGA
SPI
CPU
CPU
CS_DLY
FH
P23
INT
SLIC_INT
DPRAM
INT_CON
Local
Bus
Local
TSW
Host
Local- bus I/F
DPLL
JTAG
GAIN
Internal Highway
Internal bus
APITS
controller
HDLC
8ch
FIFO /
DPRAM
DPITS
controller
Highway
Local
Highway I/F
PT-I/F
PITS
D
GPIO-i/f
GPIO
CODEC
controller
RT_SND
8
KX-NS5170X/KX-NS5170SX
• Local highway interface
Accommodates 2.048, 4.096, and 8.192MHz highways (Up to 64 time slots).
• Local gain control
Controls the gain of the local highway up-and-down 64ch in 1db step arbitrarily.
• Local TSW
Exchanges the time slots between CT bus (1024ch) and local highway (64ch).
• Local gain control
Controls the gain of the local highway up-and-down 64ch in 1db step arbitrarily.
• PT interface
Allows APT/DPT interface to be selected for each port.
• CODEC interface
Can connect up to four Infineon-manufactured PEB2466, and is intended for enabling the line control.
• GPIO interface
Parallel interface that is arbitrarily programmable bidirectionally.
5.2.2.
Line-System Circuit
5.2.2.1.
PT Interface
• APT data communications
Control data is transmitted from the DTL terminal of ASIC, then is output to APT (between D1 and D2) by way of the driver U105
and the pulse transformer T100.
The control data transmitted from APT is input to the DR terminal of ASIC by way of the pulse transformer T100 and R126.
ASIC compares VREF+ with the input waveform, and receives a valid pulse.
and the pulse transformer T100.
The control data transmitted from APT is input to the DR terminal of ASIC by way of the pulse transformer T100 and R126.
ASIC compares VREF+ with the input waveform, and receives a valid pulse.
• DPT data communications
Bch/Dch/Cch data is transmitted from the DTL/DTH terminal of ASIC, and the AMI-converted pulse signal is output to
DPT (between D1 and D2) by way of the driver U105 and the pulse transformer T100.
The Bch/Dch/Cch data transmitted from APT is input to the DR terminal of ASIC by way of the pulse transformer T100 and R126.
ASIC compares VREF+ and VREF- with the input wave- form, and receives a valid pulse.
DPT (between D1 and D2) by way of the driver U105 and the pulse transformer T100.
The Bch/Dch/Cch data transmitted from APT is input to the DR terminal of ASIC by way of the pulse transformer T100 and R126.
ASIC compares VREF+ and VREF- with the input wave- form, and receives a valid pulse.
• Bch communications
Communicated by the PCM data (64kbps Å~ 2) connected from the local highway by ASIC.
Used mainly for the audio signal of DPT.
Used mainly for the audio signal of DPT.
• Dch communications
Communicated by the data (16kbps) protocol-converted by the HDLC controller in ASIC.
Used mainly for the control signal of DPT.
Used mainly for the control signal of DPT.
• Cch communications
Communicated by the data (8kbps) converted by the serial/parallel-converting circuit in ASIC.
Used mainly for recognizing the terminal model.
Used mainly for recognizing the terminal model.
DG
DTH[0]
C105A
DTL[0]
DG
C104A
R127A
C103A
R125A
DG
R123A
DR[0]
R122A
R120A
+5V
R121A
R124A
T100A
1
2
4
5
6
7
10
9
8
C107A
C106A
R117A
R118A
R119A
R126A
C102A
U105A
5
3
4
U105A
2
6
1
C108A
C109A
D1
D2
Click on the first or last page to see other KX-NS5170XSX / KX-NS5170X-SX service manuals if exist.