Panasonic KX-NS5170XSX / KX-NS5170X-SX Service Manual ▷ View online
13
KX-NS5170X/KX-NS5170SX
• Surge Protection
Thyristor is sintalled between T or R and FG protect from extraneous surge.
• Bell Signal Genarator and Transmission
In ringing mode, the ringing DC offset and the ringing signal are summed within SLIC/CODEC in accordance with the pro-
grammed values.
The SLIC/CODEC supplies the line with 65 Vrms.
The bell signal is generated with VBAT supplied to the SLIC/CODEC.
grammed values.
The SLIC/CODEC supplies the line with 65 Vrms.
The bell signal is generated with VBAT supplied to the SLIC/CODEC.
nC_INT[0]
DG
+3.3V
Q200A
R213A
R210A
R201A
R212A
TP1
R206A
DG
DG
DG
FG
R205A
C
2
0
6A
+40V
+40V
DG
C204B
C
2
13
A
R211A
+3.3V
R200A
R214A
DG
R
2
04
A
C
2
01
A
C
2
0
2A
R208A
L201B
C211A
L201A
TP2
R207A
C212A
C
2
03
A
D
2
00
A
R211B
L200B
R210B
C208A
C
2
00
A
C204A
C
2
05
A
C210A
L200A
R
2
03
A
C207A
R216A
R209A
IC200A
7
8
S
TIPDC
A
9
C
A
PP
A
10
C
A
PM
A
11
SV
B
A
T
A
DTX
DRX
SDCHA
SDCLA
DCDRVA
DCFFA
DCFFB
DCDRVB
SDCLB
DRX
SDCHA
SDCLA
DCDRVA
DCFFA
DCFFB
DCDRVB
SDCLB
T
B
B
B
CB
1
2
SV
DC
13
*R
S
T
14
INTB/DT
X
ENB
SDITHRU
PCLK
PCLK
SDCHB
VDDD
VDDREG
VDDD
VDDREG
15
F
SY
NC
18
19
20
21
22
23
24
25
26
19
20
21
22
23
24
25
26
16
17
17
27
28
29
30
28
29
30
CSB
EPAD2
C210B
R
2
0
2A
TIP_A
RING_A
D
2
0
2A
D
2
03
A
B
A
VBAT for port B
VBAT for port A
R
2
0
2
B
DG
DG
+3.3V
C
2
09
A
Q200A
R213A
Q200B
R210A
R212A
TP1
R
2
03B
DG
C
2
0
2
B
C207B
R206B
DG
DG
R
2
1
7A
R205A
C
2
0
6A
DG
+40V
R208B
DG
R207B
+40V
DG
C204B
C
2
13
A
R211A
DG
R
2
04
A
DG
R
2
15
A
L201B
C
2
05B
C211A
C
2
0
6
B
L201A
TP2
R209B
C212A
C
2
03
A
C
2
13B
D
2
00
A
R211B
L200B
R210B
DG
D
2
00B
R205B
C204A
C
2
05
A
C210A
L200A
R
2
03
A
C
2
01B
IC200A
7
8
S
TIPDC
A
9
C
A
PP
A
10
C
A
PM
A
11
SV
B
A
T
A
DTX
DRX
SDCHA
SDCLA
DCDRVA
DCFFA
DCFFB
DCDRVB
SDCLB
DRX
SDCHA
SDCLA
DCDRVA
DCFFA
DCFFB
DCDRVB
SDCLB
33
S
DI
34
SV
B
A
TB
35
C
A
PMB
3
6
C
A
PPB
3
7
IREF
38
S
TIPDCB
39
1
2
SV
DC
13
*R
S
T
14
INTB/DT
X
ENB
SDITHRU
PCLK
SDCHB
VDDD
VDDREG
VDDD
VDDREG
31
S
CLK
3
2
S
DO
15
F
SY
NC
18
19
20
21
22
23
24
25
26
19
20
21
22
23
24
25
26
16
17
17
27
28
29
30
28
29
30
CSB
EPAD2
C210B
R
2
0
2A
C208B
R
2
04B
14
KX-NS5170X/KX-NS5170SX
• EXT-CID Transmission
The SLIC/CODEC generates the extension Caller ID signals (FSK signal) with the CPU board control.
The data flow is shown below.
The data flow is shown below.
1. The CPU board control signals are received.
2. PLD controls the tone generator inside SLIC/CODEC.
3. The SLIC/CODEC generates Caller ID signals (FSK).
4. Caller ID signals are sent to extension ports.
2. PLD controls the tone generator inside SLIC/CODEC.
3. The SLIC/CODEC generates Caller ID signals (FSK).
4. Caller ID signals are sent to extension ports.
DLC FPGA
(IC404)
SLIC/CODEC
(IC200A-C)
CPU Interface
FSK Signal (Analog Signal)
TONE
FSK
TONE1
TONE2
TONE=OFF
15
KX-NS5170X/KX-NS5170SX
5.2.3.
Power Supply Circuit
The input from the main power supply is in 2 voltage levels: +3.3V, +40V.
Each required voltage levels are generated on board DC-DC converter.
Power supply block diagram is described as below figure.
Each required voltage levels are generated on board DC-DC converter.
Power supply block diagram is described as below figure.
DCDC
SLIC/CODEC
DLC FPGA
ROM/RAM
ASIC
SLIC/CODEC
Vbat
DCDRV
SLT Power Supply
Bell Signal
MW
Bell Signal
MW
+3.3V
+40V Input
+3.3V Input
DCDC
DCDC
+15V
+5V
DPT(+40V) Power Supply
DPT(+15V)/APT Power Supply
Pulse Transformer
LDO
LDO
DLC FPGA
DLC FPGA
+2.5V
+1.2V
16
KX-NS5170X/KX-NS5170SX
6 Location of Controls and Components
6.1.
Names and Locations
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