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Fig.2 shows detail block diagram of CPU Board (MPR) , and each function of CPU Board (MPR) is described in Table.4.

Device/Function Block

Description

CPU

CPU controls exchange and monitoring functions of the whole NS500 system.

DDR3

DDR3 is main memory of CPU Board (MPR). Operating system, application program and concerning data are
stored in this memory.

NAND Flash

Program and system data are stored in this memory.

SRAM

SRAM is backed up by battery, and system information is stored this non-volatilized memory.

ASIC

ASIC provides basic PBX function such as time switch, tone generation and so on.

USB

USB master port for maintenance.

L2SW/LAN(RJ45)

LAN port is used for VoIP and Web-MC connection.

SD Card

UM voice data are stored in this SD card.

RTC

RTC is battery backed up clock which maintains system clock of NS500 system.

ARM

Cortex- A8

600MHz

L1 32K/32K

w/SED

L2 256K w/ECC

176K ROM

64K RAM

64K RAM

Crypto

DDR

Interface

DDR3

512MB

NAND

NAND

FLASH

512MB

UART

McASP

Ethernet

USB

SD

GPIO

Interrupt

etc.

DC/DC(+3.3V,+1.8V,+1.1V)

I2C

AC_ALM, DC_ALM, System Reset, FPGA_REBOOT, DONE

EXP- M

Connector

DSP

o

pti

o

n

Con

nec

tor

RMT

Opt

io

n

Con

nec

tor

ASIC1

Master
Mode

USB

TypeA

LAN

RJ45

RMII

USB- Host- I/F

SRAM

512KB

LED

RTC

+5V

External bus

ER,DR

SL

IDE SW

SD- I/F

8

0

P

IN
C

O

N

NE

C

T

O

R
(C

PU

In

te

rf

a

c

e

)

TDM

L2SW

PHY

ST

A

T

US

PBX

 MO

D

E

PHY

PHY

DC/DC

+3.3V

+15V

8bit

8bit

16bit

SD- Card

Connector

16bit

+5V

+VBAT

Exp

ansi

on

 bu

s

UART- I/F

+5V

Fig.2 CPU Board (MPR) Block Diagram

6

Fig.3 shows detail block diagram of Mother Board, and each function of Base is described in Table.5.

Device/Function Block

Description

ASIC2

ASIC2 controls SLIC/CODEC LSI of each analog line port and the trunk controller DSP which is used in each 
analog trunk port.

SLIC/CODEC

SLIC/CODEC is exclusive LSI which is used for analog line interface.
  1) Line interface power supply
  2) Dial pulse detection
  3) DTMF receiver / Caller ID generation
  4) Bell signal generation
  5) Hooking detection / Ringtrip detection
  6) 2W/4W conversion
  7) CODEC function

DSP(CO)

DSP(CO) is exclusive LSI which is used analog trunk port.
  1) Dial pulse generation
  2) DTMF signal generation / Caller ID detection
  3) Bell signal detection
  4) CPC signal detection
  5) 2W/4W conversion
  6) CODEC function

DPT I/F

DPT I/F is Digital Line Interface.

6

Trunk option

Connector

Extension option

Connector

8

0

P

IN
C

O

N

NE

C

T

O

R
(C

PU

In

te

rf

a

c

e

)

RJ45
MOH

PAG

RJ45

RJ45

POWER I/F

Connector

Exp

ansi

on

 bu

s

SLIC/CODEC bus (SPI)

TDM Highway bus

AFE

DSP

(2ch)

AFE

AFE

SLIC/CODEC(2ch)

AFE

AFE

AFE

AFE

AFE

AFE

AFE

SLIC/CODEC(2ch)

SLIC/CODEC(2ch)

SLIC/CODEC(2ch)

SLIC/CODEC(2ch)

SLIC/CODEC(2ch)

SLIC/CODEC(2ch)

SLIC/CODEC(2ch)

DPT

I/F

(2ch)

DSP

(2ch)

ACALM, DCALM

+40V, GND

+15V, GND

Dial Pulse, CPC DET

Dial Pulse, CPC DET

RJ45

RJ45

RJ45

IIO bus

DSP

(2ch)

AFE

Dial Pulse, CPC DET

DPT- I/F

FAN I/F

Connector

VBAT

+15V, GND

INT(2)

DC/DC

+3.3 V, GND

15

12V

INT_SLIC

INT_DSP

INT_EXT

INT_CO

FAN_ALM

RJ45
MOH

PAG

RJ45
MOH

PAG

CO1-CO2

CO2-CO3

CO4-CO5

Re
la

y

RJ45

SLT2
SLT1

Fig.3 Main Unit Mother Board Block Diagram

ASIC2
Line
Controller

7

Fig.4 shows detail block diagram of CPU Board (SPR), and each function of CPU Board (SPR) is described in Table.6.

Card

Description

CPU

CPU controls the line card in the expansion unit by the control from an CPU Board (MPR).

DDR3

DDR3 is main memory of CPU Board (SPR). Operating system, application program and concerning data are
stored in this memory.

NAND Flash

CPU program is stored in this memory.

ASIC

ASIC provides control and monitoring function of each line card.

 

ARM

Cortex- A8

300MHz

L1 32K/32K

w/SED

L2 256K w/ECC

176K ROM

64K RAM

64K RAM

Crypto

DDR

Interface

DDR3

128MB

NAND

NAND

FLASH

256MB

UART

SD

GPIO

Interrupt

etc.

DC/DC(+3.3V,+1.8V,+1.1V)

AC_ALM, DC_ALM, System Reset, FPGA_REBOOT, DONE

ASIC1
Slave
Mode

LED

+5V

External bus

8

0

P

IN
C

O

N

NE

C

T

O

R
(C

PU

In

te

rf

a

c

e

)

ST

A

T

US

DC/DC

+3.3V

+15V

8bit

8bit

+5V

+VBAT

LVDS

Down

Highway

Up
Highway

FH+CLK

(8MHz)

Interrupt

Exp I/F

RJ45

NETREF

Exp

ansi

on

 bu

s

Fig.4 CPU Board (SPR) Block Diagram

8

Fig.5 shows detail block diagram of Mother Board, and each function of Base is described in Table.7.

Device/Function Block

Description

ASIC

ASIC controls and monitors SLIC/CODEC LSI of each analog line port.

SLIC/CODEC

SLIC/CODEC is exclusive LSI which is used for analog line interface.
    8) Line interface power supply
    9) Dial pulse detection
  10) DTMF receiver / Caller ID generation
  11) Bell signal generation
  12) Hooking detection / Ringtrip detection
  13) 2W/4W conversion
  14) CODEC function

Trunk option

Connector

Extension option

Connector

8

0

P

IN
C

O

N

NE

C

T

O

R
(C

PU

In

te

rf

a

c

e

)

RJ45

POWER I/F

Connector

Exp

ansi

on

 bu

s

SLIC/CODEC bus (SPI)

TDM Highway bus

AFE

SLIC/CODEC(2ch)

AFE

AFE

AFE

AFE

AFE

AFE

AFE

SLIC/CODEC(2ch)

SLIC/CODEC(2ch)

SLIC/CODEC(2ch)

SLIC/CODEC(2ch)

SLIC/CODEC(2ch)

SLIC/CODEC(2ch)

SLIC/CODEC(2ch)

ACALM, DCALM

+40V, GND

+15V, GND

RJ45

RJ45

RJ45

ASIC2
Line Controller

FAN I/F

Connector

+15V, GND

INT(2)

DC/DC

+3.3 V, GND

15

12V

INT_SLIC

INT_EXT

INT_CO

FAN_ALM

RJ45

PFT

RJ45

PFT

PFT1-PFT2

PFT2-PFT3

SLT4
SLT3

Re
la

y

To SLT3-SLT4
PFT Relay

RJ45

SLT2
SLT1

Fig.5 Expansion Unit Mother Board Block Diagram