Panasonic KX-NCV200BX / KX-TVM204X / KX-TVM296X (serv.man3) Service Manual ▷ View online
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KX-NCV200BX / KX-TVM204X / KX-TVM296X
15.2.1.2. DSP and DPT Block Diagram
McBSP0 sends and receives voice PCM data to and from the PBX interface. The PBX interface has three types of interfaces.
For this reason, each interface has a different device to and from which PCM voice data are sent and received. In any case, the
DSP's McBSP0 is a clock slave while the clock master varies from interface to interface. *In the case of 1 and 3, the clock mas-
ter is the ASIC. In the case of 2, the clock master is the DPT I/F. The base clock is a 2-MHz PCM serial communication signal,
and voice data of up to 24 channels are sent and received. As for the placements of clock master and clock slave, see the refer-
ences at the end of the chapter.
McBSP1 sends and receives the data compressed between the ASIC and the DSP and the data decompressed by the DSP.
The DSP is a clock slave, and the clock master is the ASIC. McBSP1 forms the serial communication that sends and receives
16-bit command data and 16-bit data on the base clock 8 MHz respectively with 24 channels x 2 (mainframe + subframe) = 48
frames.
The HPI-8 is accessed by the CPU and it writes the command setting program data into the DSP.
The CPU has a mechanism at startup to download application programs to each DSP's internal RAM with the HPI-8. With this
configuration, application programs can be uploaded as necessary after installation.
The DSP unit installed in this system has four channels per unit, and two DSPs are installed.
For this reason, each interface has a different device to and from which PCM voice data are sent and received. In any case, the
DSP's McBSP0 is a clock slave while the clock master varies from interface to interface. *In the case of 1 and 3, the clock mas-
ter is the ASIC. In the case of 2, the clock master is the DPT I/F. The base clock is a 2-MHz PCM serial communication signal,
and voice data of up to 24 channels are sent and received. As for the placements of clock master and clock slave, see the refer-
ences at the end of the chapter.
McBSP1 sends and receives the data compressed between the ASIC and the DSP and the data decompressed by the DSP.
The DSP is a clock slave, and the clock master is the ASIC. McBSP1 forms the serial communication that sends and receives
16-bit command data and 16-bit data on the base clock 8 MHz respectively with 24 channels x 2 (mainframe + subframe) = 48
frames.
The HPI-8 is accessed by the CPU and it writes the command setting program data into the DSP.
The CPU has a mechanism at startup to download application programs to each DSP's internal RAM with the HPI-8. With this
configuration, application programs can be uploaded as necessary after installation.
The DSP unit installed in this system has four channels per unit, and two DSPs are installed.
*There are three types of interfaces to connect a VM to a PBX.
1: APT Interface (TVM50 Only)
2: DPT Interface
3: VM-Link Interface (NCV200 Only)
2: DPT Interface
3: VM-Link Interface (NCV200 Only)
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KX-NCV200BX / KX-TVM204X / KX-TVM296X
• McBSP0
McBSP0 is used at the serial communication port for sending/receiving voice data between the CODEC and the DSP, and
between the PBX interface and the DSP.
between the PBX interface and the DSP.
As for the data to be handled, only 2-channel 8-bit MSB First voice data are sent and received. The frame pulse remains active
during valid data are asserted according to the specifications of the PBX interface ASIC. There is no data delay in frame pulses
and data sent and received.
during valid data are asserted according to the specifications of the PBX interface ASIC. There is no data delay in frame pulses
and data sent and received.
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KX-NCV200BX / KX-TVM204X / KX-TVM296X
• McBSP1
McBSP1 is connected with the serial management controller interface of VM-dedicated ASIC.
This interface sends and receives the voice data and control commands of each channel with up to 12 DSPs (24 channels) at the
maximum. The serial communication format to be connected is shown below. The DSP operates as a clock slave even at
McBSP1, and the clock master is the ASIC dedicated to VM. The base clock's CLKR/X is set at 8.192 MHz, and the frame sync-
pulse at 2 KHz. As for the frame pulse, only one cycle of clock becomes active. The DSP is set to allow data to lag one bit behind
the assertion of frame pulse. Each channel's command data 16 bits and voice data 16 bits are arranged as mainframe and sub-
frame, and 48 frames of 24 channels are time-shared and arranged on this serial communication format.
Each DSP sends and receives commands and data of two channels of serial communication signals. As DFH 1-12 signals that
show the dedicated data frame heads are input into each DSP, each DSP sends and receives data to and from these DFH sig-
nals through 4-word frame, single-phase frame and 32-bit words (which can be changed, depending on temporary DSP specifi-
cations). With DFH input, each DSP handles 24 x 2 x (16 +16) = 1536 bits as valid data. As for the frame format of command
frames, see ASIC module specifications. The frame format of data frames is composed of 16-bit MSB First. The clock between
McBSP0 and McBSP1 is not synchronized.
This interface sends and receives the voice data and control commands of each channel with up to 12 DSPs (24 channels) at the
maximum. The serial communication format to be connected is shown below. The DSP operates as a clock slave even at
McBSP1, and the clock master is the ASIC dedicated to VM. The base clock's CLKR/X is set at 8.192 MHz, and the frame sync-
pulse at 2 KHz. As for the frame pulse, only one cycle of clock becomes active. The DSP is set to allow data to lag one bit behind
the assertion of frame pulse. Each channel's command data 16 bits and voice data 16 bits are arranged as mainframe and sub-
frame, and 48 frames of 24 channels are time-shared and arranged on this serial communication format.
Each DSP sends and receives commands and data of two channels of serial communication signals. As DFH 1-12 signals that
show the dedicated data frame heads are input into each DSP, each DSP sends and receives data to and from these DFH sig-
nals through 4-word frame, single-phase frame and 32-bit words (which can be changed, depending on temporary DSP specifi-
cations). With DFH input, each DSP handles 24 x 2 x (16 +16) = 1536 bits as valid data. As for the frame format of command
frames, see ASIC module specifications. The frame format of data frames is composed of 16-bit MSB First. The clock between
McBSP0 and McBSP1 is not synchronized.
• McBSP2
For this DSP, McBSP2 is unassigned and used as general-purpose I/O. Depending on the slots installed, the DSP must recog-
nize which channel it now falls under. Therefore, the serial communication function of McBSP2 is disabled, and DR, CLKS, FSR
and CLKR are used as general-purpose input ports to discriminate 12 types of channels with these four bits.
nize which channel it now falls under. Therefore, the serial communication function of McBSP2 is disabled, and DR, CLKS, FSR
and CLKR are used as general-purpose input ports to discriminate 12 types of channels with these four bits.
Table: Channel Identification Bit Assignment
CLKR signals for the two DSPs installed in the unit are set and fixed as follows: The DSP A: CLKR = 0, DSP B: CLKR = 1.
Depending on the slots to be installed, FSR, DR and CLKX are dynamically set.
DX pins are used as output pins for the signals to control LED that shows the status of DSP.
At the time of Power ON normal: DX=High, Err, and at the time of Power DOWN: DX=Low.
The remaining pin FSX must be kept capable, as input, of reading the status from CPU.
Depending on the slots to be installed, FSR, DR and CLKX are dynamically set.
DX pins are used as output pins for the signals to control LED that shows the status of DSP.
At the time of Power ON normal: DX=High, Err, and at the time of Power DOWN: DX=Low.
The remaining pin FSX must be kept capable, as input, of reading the status from CPU.
Pin No.
Ch1
Ch2
Ch2
Ch3
Ch4
Ch4
Ch5
Ch6
Ch6
Ch7
Ch8
Ch8
Ch9
Ch10
Ch11
Ch12
Ch13
Ch14
Ch14
Ch15
Ch16
Ch16
Ch17
Ch18
Ch18
Ch19
Ch20
Ch20
Ch21
Ch22
Ch22
Ch23
Ch24
Ch24
42
CLKR
0
1
0
1
0
1
0
1
0
1
0
1
44
FSR
1
1
0
0
1
1
0
0
1
1
0
0
47
DR
0
0
1
1
1
1
0
0
0
0
1
1
49
CLKX
0
0
0
0
0
0
1
1
1
1
1
1
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KX-NCV200BX / KX-TVM204X / KX-TVM296X
• HPI-8
The HPI-8 is controlled directly by the CPU, and performs command settings from the CPU to the DSP, FIFO-style command
sending and receiving such as DSP status reads, and DSP program downloads on system startups or software updates. Pro-
gram downloads are carried out through the HPI-8 on system startup by directly writing to the DSP's on-chip RAM from the host
CPU. Upon DSP startup it is in HPI boot mode.
(1) Host Interface
Between the DSP and the host CPU, DSP on-chip RAM area is accessed through the HPI. The CPU sets the DSP's registers,
and the DSP exchanges status information and various data with the CPU.
The connection between the DSP's HPI external interface pin and the host CPU is shown below.
sending and receiving such as DSP status reads, and DSP program downloads on system startups or software updates. Pro-
gram downloads are carried out through the HPI-8 on system startup by directly writing to the DSP's on-chip RAM from the host
CPU. Upon DSP startup it is in HPI boot mode.
(1) Host Interface
Between the DSP and the host CPU, DSP on-chip RAM area is accessed through the HPI. The CPU sets the DSP's registers,
and the DSP exchanges status information and various data with the CPU.
The connection between the DSP's HPI external interface pin and the host CPU is shown below.
There can be as many as 12 on-board DSP's. The interrupt signals from 12 DSP's are sent to the HPI control interface of the
ASIC. Through this signal, an interrupt flag is asserted to the appropriate channel of the HPI interrupt register in the ASIC. At the
same time, an HPI interrupt signal notification is sent to the host CPU from the ASIC. The CPU which received the notification of
the HPI interrupt signal immediately reads the appropriate channel of the HPI interrupt register in the ASIC, clears the register,
and at the same time performs access to the DSP that sent the interrupt.
DSP
ASIC. Through this signal, an interrupt flag is asserted to the appropriate channel of the HPI interrupt register in the ASIC. At the
same time, an HPI interrupt signal notification is sent to the host CPU from the ASIC. The CPU which received the notification of
the HPI interrupt signal immediately reads the appropriate channel of the HPI interrupt register in the ASIC, clears the register,
and at the same time performs access to the DSP that sent the interrupt.
DSP
→ HOST CPU
When data or status changes that require signaling to the host occur, the HINT bit of the HPIC register above is asserted,
causing an assertion to the DSP chip's / HINT external terminal. In concordance with this, the ASIC and host CPU perform
appropriate tasks such as reading designated registers of the DSP.
causing an assertion to the DSP chip's / HINT external terminal. In concordance with this, the ASIC and host CPU perform
appropriate tasks such as reading designated registers of the DSP.
HOST CPU
→ DSP
When data transference becomes necessary from the host to the DSP, the CPU writes to the designated register, after which
DSPINT is asserted to the HPIC register, sending an interrupt to the DSP. In concordance with this interrupt, the DSP per-
forms appropriate task processing such as reading designated registers.
DSPINT is asserted to the HPIC register, sending an interrupt to the DSP. In concordance with this interrupt, the DSP per-
forms appropriate task processing such as reading designated registers.
• Reset
The DSP reset signal has individual reset signal capability, and performs system reset at POWER ON in addition to resets to
each DSP chip independently.
each DSP chip independently.
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