Panasonic KX-NCP1104XJ (serv.man2) Service Manual ▷ View online
29
KX-NCP1104XJ
85
6
E21
PCI_AD01
PCI_AD01
HBD01
I/O
I/
Opsts33
Opsts33
PCI_AD01: Same as PCI_AD00.
HBD01: Same as HBD00.
HBD01: Same as HBD00.
86
7
E20
PCI_AD02
PCI_AD02
HBD02
I/O
I/
Opsts33
Opsts33
PCI_AD02: Same as PCI_AD00.
HBD02: Same as HBD00.
HBD02: Same as HBD00.
87
8
E19
PCI_AD03
PCI_AD03
HBD03
I/O
I/
Opsts33
Opsts33
PCI_AD03: Same as PCI_AD00.
HBD03: Same as HBD00.
HBD03: Same as HBD00.
88
9
E22
PCI_AD04
PCI_AD04
HBD04
I/O
I/
Opsts33
Opsts33
PCI_AD04: Same as PCI_AD00.
HBD04: Same as HBD00.
HBD04: Same as HBD00.
89
10
F21
PCI_AD05
PCI_AD05
HBD05
I/O
I/
Opsts33
Opsts33
PCI_AD05: Same as PCI_AD00.
HBD05: Same as HBD00.
HBD05: Same as HBD00.
90
11
F20
PCI_AD06
PCI_AD06
HBD06
I/O
I/
Opsts33
Opsts33
PCI_AD06: Same as PCI_AD00.
HBD06: Same as HBD00.
HBD06: Same as HBD00.
91
12
F19
PCI_AD07
PCI_AD07
HBD07
I/O
I/
Opsts33
Opsts33
PCI_AD07: Same as PCI_AD00.
HBD07: Same as HBD00.
HBD07: Same as HBD00.
92
13
G21
PCI_AD08
PCI_AD08
HBD08
I/O
I/
Opsts33
Opsts33
PCI_AD08: Same as PCI_AD00.
HBD08: Same as HBD00.
HBD08: Same as HBD00.
93
14
G20
PCI_AD09
PCI_AD09
HBD09
I/O
I/
Opsts33
Opsts33
PCI_AD09: Same as PCI_AD00.
HBD09: Same as HBD00.
HBD09: Same as HBD00.
94
15
G22
PCI_AD10
PCI_AD10
HBD10
I/O
I/
Opsts33
Opsts33
PCI_AD10: Same as PCI_AD00.
HBD10: Same as HBD00.
HBD10: Same as HBD00.
95
16
G19
PCI_AD11
PCI_AD11
HBD11
I/O
I/
Opsts33
Opsts33
PCI_AD11: Same as PCI_AD00.
HBD11: Same as HBD00.
HBD11: Same as HBD00.
96
17
H21
PCI_AD12
PCI_AD12
HBD12
I/O
I/
Opsts33
Opsts33
PCI_AD12: Same as PCI_AD00.
HBD12: Same as HBD00.
HBD12: Same as HBD00.
97
18
H22
PCI_AD13
PCI_AD13
HBD13
I/O
I/
Opsts33
Opsts33
PCI_AD13: Same as PCI_AD00.
HBD13: Same as HBD00.
HBD13: Same as HBD00.
98
19
H20
PCI_AD14
PCI_AD14
HBD14
I/O
I/
Opsts33
Opsts33
PCI_AD14: Same as PCI_AD00.
HBD14: Same as HBD00.
HBD14: Same as HBD00.
99
20
H19
PCI_AD15
PCI_AD15
HBD15
I/O
I/
Opsts33
Opsts33
PCI_AD15: Same as PCI_AD00.
HBD15: Same as HBD00.
HBD15: Same as HBD00.
100
21
L20
PCI_AD16
PCI_AD16
HBD16
I/O
I/
Opsts33
Opsts33
PCI_AD16: Same as PCI_AD00.
HBD16: Same as HBD00.
HBD16: Same as HBD00.
101
22
L19
PCI_AD17
PCI_AD17
HBD17
I/O
I/
Opsts33
Opsts33
PCI_AD17: Same as PCI_AD00.
HBD17: Same as HBD00.
HBD17: Same as HBD00.
102
23
M21
PCI_AD18
PCI_AD18
HBD18
I/O
I/
Opsts33
Opsts33
PCI_AD18: Same as PCI_AD00.
HBD18: Same as HBD00.
HBD18: Same as HBD00.
103
24
M22
PCI_AD19
PCI_AD19
HBD19
I/O
I/
Opsts33
Opsts33
PCI_AD19: Same as PCI_AD00.
HBD19: Same as HBD00.
HBD19: Same as HBD00.
104
25
M20
PCI_AD20
PCI_AD20
HBD20
I/O
I/
Opsts33
Opsts33
PCI_AD20: Same as PCI_AD00.
HBD20: Same as HBD00.
HBD20: Same as HBD00.
105
26
N22
PCI_AD21
PCI_AD21
HBD21
I/O
I/
Opsts33
Opsts33
PCI_AD21: Same as PCI_AD00.
HBD21: Same as HBD00.
HBD21: Same as HBD00.
106
27
M19
PCI_AD22
PCI_AD22
HBD22
I/O
I/
Opsts33
Opsts33
PCI_AD22: Same as PCI_AD00.
HBD22: Same as HBD00.
HBD22: Same as HBD00.
107
28
P22
PCI_AD23
PCI_AD23
HBD23
I/O
I/
Opsts33
Opsts33
PCI_AD23: Same as PCI_AD00.
HBD23: Same as HBD00.
HBD23: Same as HBD00.
108
29
P20
PCI_AD24
PCI_AD24
HBD24
I/O
I/
Opsts33
Opsts33
PCI_AD24: Same as PCI_AD00.
HBD24: Same as HBD00.
HBD24: Same as HBD00.
109
30
P19
PCI_AD25
PCI_AD25
HBD25
I/O
I/
Opsts33
Opsts33
PCI_AD25: Same as PCI_AD00.
HBD25: Same as HBD00.
HBD25: Same as HBD00.
110
31
R21
PCI_AD26
PCI_AD26
HBD26
I/O
I/
Opsts33
Opsts33
PCI_AD26: Same as PCI_AD00.
HBD26: Same as HBD00.
HBD26: Same as HBD00.
111
32
R20
PCI_AD27
PCI_AD27
HBD27
I/O
I/
Opsts33
Opsts33
PCI_AD27: Same as PCI_AD00.
HBD27: Same as HBD00.
HBD27: Same as HBD00.
112
33
R19
PCI_AD28
PCI_AD28
HBD28
I/O
I/
Opsts33
Opsts33
PCI_AD28: Same as PCI_AD00.
HBD28: Same as HBD00.
HBD28: Same as HBD00.
113
34
T21
PCI_AD29
PCI_AD29
HBD29
I/O
I/
Opsts33
Opsts33
PCI_AD29: Same as PCI_AD00.
HBD29: Same as HBD00.
HBD29: Same as HBD00.
114
35
U22
PCI_AD30
PCI_AD30
HBD30
I/O
I/
Opsts33
Opsts33
PCI_AD30: Same as PCI_AD00.
HBD30: Same as HBD00.
HBD30: Same as HBD00.
115
36
T20
PCI_AD31
PCI_AD31
HBD31
I/O
I/
Opsts33
Opsts33
PCI_AD31: Same as PCI_AD00.
HBD31: Same as HBD00.
HBD31: Same as HBD00.
Total
Signals
Interface
Signals
Pin
PCI &
µP Bus Interface Signal Name Pin Com-
patible Mode and Enhanced Feature Mode
Signal
Type
I/O Type
Signal Description
PCI Bus -
Peripheral
Mode
PCI Bus - Host
Mode
uP Bus Mode
30
KX-NCP1104XJ
116
37
F22
PCI_CBE0#
PCI_CBE0#
HBBE0#/
HBA0
HBA0
I/O
I/
Opsts33
Opsts33
PCI_CBE0#: Bus Command and Byte Enable. Bus
Command and Byte Enables are multiplexed on the
same PCI pins. During the address phase of a trans-
action, CBE[3:0]# defines the bus command. During
the data phase, CBE[3:0]# is used as Byte Enables.
Connect to PCI Bus: CBE[3:0]#.
HBBE0#/HBA0: Microprocessor Bus Byte Enables
or Address Bit 0. Connect to Microprocessor Bus
Byte Enable [3:0] (low active) or Address Bit 0.
HBBE3# = 0 indicates HBD[31: 24] is active in the
data transfer.
HBBE2# = 0 indicates HBD[23: 16] is active in the
data transfer.
HBBE1# = 0 indicates HBD[15: 8] is active in the
data transfer.
HBBE0# = 0 indicates HBD[7: 0] is active in the data
transfer.
When HB_BUS_SIZE[1:0] = 01 (16-bit data bus),
HBBE3# and HBBE2# are unused and must be tied
high.
When HB_BUS_SIZE[1:0] = 00 (8-bit data bus),
HBBE0# becomes HBA[0] and must be connected
to address bit 0 of the microprocessor, and
HBBE3#, HBBE2#, and HBBE1# must be tied high.
When HBBE0#/HBA00 is low, the data bus transfers
bits [7:0], and when HBBE0#/HBA00 is high, the
data bus transfers bits [15:8].
Command and Byte Enables are multiplexed on the
same PCI pins. During the address phase of a trans-
action, CBE[3:0]# defines the bus command. During
the data phase, CBE[3:0]# is used as Byte Enables.
Connect to PCI Bus: CBE[3:0]#.
HBBE0#/HBA0: Microprocessor Bus Byte Enables
or Address Bit 0. Connect to Microprocessor Bus
Byte Enable [3:0] (low active) or Address Bit 0.
HBBE3# = 0 indicates HBD[31: 24] is active in the
data transfer.
HBBE2# = 0 indicates HBD[23: 16] is active in the
data transfer.
HBBE1# = 0 indicates HBD[15: 8] is active in the
data transfer.
HBBE0# = 0 indicates HBD[7: 0] is active in the data
transfer.
When HB_BUS_SIZE[1:0] = 01 (16-bit data bus),
HBBE3# and HBBE2# are unused and must be tied
high.
When HB_BUS_SIZE[1:0] = 00 (8-bit data bus),
HBBE0# becomes HBA[0] and must be connected
to address bit 0 of the microprocessor, and
HBBE3#, HBBE2#, and HBBE1# must be tied high.
When HBBE0#/HBA00 is low, the data bus transfers
bits [7:0], and when HBBE0#/HBA00 is high, the
data bus transfers bits [15:8].
117
38
J21
PCI_CBE1#
PCI_CBE1#
HBBE1#
I/O
I/
Opsts33
Opsts33
PCI_CBE1#: Same as PCI_CBE0#.
HBBE1#: Same as HBBE0#.
HBBE1#: Same as HBBE0#.
118
39
L22
PCI_CBE2#
PCI_CBE2#
HBBE2#
I/O
I/
Opsts33
Opsts33
PCI_CBE2#: Same as PCI_CBE0.
HBBE2#: Same as HBBE0.
HBBE2#: Same as HBBE0.
119
40
R22
PCI_CBE3#
PCI_CBE3#
HBBE3#
I/O
I/
Opsts33
Opsts33
PCI_CBE3#: Same as PCI_CBE0.
HBBE3#: Same as HBBE0.
HBBE3#: Same as HBBE0.
120
41
T22
PCI_CLK
PCI_CLK
HBCLK
I
I/
Opsts33
Opsts33
PCI_CLK: PCI Bus Clock. The PCI_CLK (PCI Bus
CLK signal) input provides timing for all transactions
on PCI. Connect to PCI CLK.
HBCLK: Microprocessor Bus Clock. The HBCLK
signal input provides timing for all transactions on
the Microprocessor Bus.
Connect to Microprocessor Bus CLK.
CLK signal) input provides timing for all transactions
on PCI. Connect to PCI CLK.
HBCLK: Microprocessor Bus Clock. The HBCLK
signal input provides timing for all transactions on
the Microprocessor Bus.
Connect to Microprocessor Bus CLK.
121
42
K21
PCI_DEVSEL# PCI_DEVSEL# HBA3
I/O
I/
Opsts33
Opsts33
PCI_DEVSEL#: Device Select. When actively
driven, DEVSEL# indicates the driving device has
decoded its address as the target of the current
access. As an input, DEVSEL# indicates whether
any device on the bus has been selected. Connect
to PCI Bus: DEVSEL#.
HBA3: Microprocessor Bus Address Bit. Same as
HBA2.
driven, DEVSEL# indicates the driving device has
decoded its address as the target of the current
access. As an input, DEVSEL# indicates whether
any device on the bus has been selected. Connect
to PCI Bus: DEVSEL#.
HBA3: Microprocessor Bus Address Bit. Same as
HBA2.
122
43
L21
PCI_FRAME#
PCI_FRAME# HBA4
I/O
I/
Opsts33
Opsts33
PCI_FRAME#: Cycle Frame. FRAME# is driven by
the current master to indicate the beginning and
duration of an access.
Connect to PCI Bus: FRAME#.
HBA4: Microprocessor Bus Address Bit. Same as
HBA2.
the current master to indicate the beginning and
duration of an access.
Connect to PCI Bus: FRAME#.
HBA4: Microprocessor Bus Address Bit. Same as
HBA2.
123
44
V22
PCI_GNT#
PCI_GNT1#
HBBLAST#
I/O
Iu/Ots8 PCI_GNT1#: Grant. GNT# is used to indicate to the
agent that access to the bus has been granted. Con-
nect to PCI Bus: GNT#.
HBBLAST#: Microprocessor Bus Burst Last Indica-
tor. Low active. Connect to Microprocessor Bus
Burst Last Indicator.
HBBLAST# = 0 indicates that the current data is the
last of the burst transfer.
nect to PCI Bus: GNT#.
HBBLAST#: Microprocessor Bus Burst Last Indica-
tor. Low active. Connect to Microprocessor Bus
Burst Last Indicator.
HBBLAST# = 0 indicates that the current data is the
last of the burst transfer.
124
45
P21
PCI_IDSEL
PCI_IDSEL
HBA5
I
I/
Opsts33
Opsts33
PCI_IDSEL: Initialization Device. IDSEL input is
used as a chip select during configuration read and
write transactions. Connect to PCI Bus: IDSEL.
HBA5: Same as HBA2.
used as a chip select during configuration read and
write transactions. Connect to PCI Bus: IDSEL.
HBA5: Same as HBA2.
Total
Signals
Interface
Signals
Pin
PCI &
µP Bus Interface Signal Name Pin Com-
patible Mode and Enhanced Feature Mode
Signal
Type
I/O Type
Signal Description
PCI Bus -
Peripheral
Mode
PCI Bus - Host
Mode
uP Bus Mode
31
KX-NCP1104XJ
125
46
V21
PCI_INTA#
Reserved
HBINT#
O
I/
Opsts33
Opsts33
PCI_INTA#: Interrupt A. INTA# is an open drain out-
put asserted to request an interrupt. Connect to PCI
Bus: INTA#. NOTE: INTA# and INTB# are NOT
used in PCI Bus - Host Mode. A GPIO(0:7) pin must
be used as the Interrupt input.
Reserved: PCI_INTA# is not used in PCI Bus - Host
Mode
HBINT#: Microprocessor Bus Interrupt. HBINT# is
an active low open drain output asserted to request
an interrupt. Connect to Microprocessor Bus INT#.
put asserted to request an interrupt. Connect to PCI
Bus: INTA#. NOTE: INTA# and INTB# are NOT
used in PCI Bus - Host Mode. A GPIO(0:7) pin must
be used as the Interrupt input.
Reserved: PCI_INTA# is not used in PCI Bus - Host
Mode
HBINT#: Microprocessor Bus Interrupt. HBINT# is
an active low open drain output asserted to request
an interrupt. Connect to Microprocessor Bus INT#.
126
47
U19
PCI_INTB#
Reserved
Reserved
O
I/
Opsts33
Opsts33
PCI_INTB#: Interrupt B (Optional). INTB# is an open
drain output asserted to request an interrupt. Con-
nect to PCI Bus: INTB#.
NOTE: INTA# and INTB# are NOT used in PCI Bus -
Host Mode. A GPIO(0:7) pin must be used as the
Interrupt input.
Reserved. Leave open.
drain output asserted to request an interrupt. Con-
nect to PCI Bus: INTB#.
NOTE: INTA# and INTB# are NOT used in PCI Bus -
Host Mode. A GPIO(0:7) pin must be used as the
Interrupt input.
Reserved. Leave open.
127
48
K19
PCI_IRDY#
PCI_IRDY#
HBA6
I/O
I/
Opsts33
Opsts33
PCI_IRDY#: Initiator Ready. IRDY# is used to indi-
cate the initiating agent’s data phase of the transac-
tion. IRDY# is used in conjunction with TRDY#.
Connect to PCI Bus: IRDY#.
HBA6: Same as HBA2.
cate the initiating agent’s data phase of the transac-
tion. IRDY# is used in conjunction with TRDY#.
Connect to PCI Bus: IRDY#.
HBA6: Same as HBA2.
128
49
J22
PCI_PAR
PCI_PAR
HBA2
I/O
I/
Opsts33
Opsts33
PCI_PAR: Parity. Parity is even parity across
AD[31:00] and CBE[3:0]#. The master drives PAR
for address and write data phases; the Bus Interface
drives PAR for read data phases.
Connect to PCI Bus: PAR.
HBA2: Microprocessor Bus Address Bits. HBA[6:2]
select registers in the Host Interface. Connect to
Microprocessor Bus Address Bits [6:2]. HBA[6] is
the most significant bit, and HBA[2] is the least sig-
nificant bit. HBA[1] is never used in the uP Host Bus,
because all of the registers are 8-bit or 16-bit and
are aligned to 32-bit word boundaries. When
HBFIFO = 1, HBA[6:2] are ignored.
AD[31:00] and CBE[3:0]#. The master drives PAR
for address and write data phases; the Bus Interface
drives PAR for read data phases.
Connect to PCI Bus: PAR.
HBA2: Microprocessor Bus Address Bits. HBA[6:2]
select registers in the Host Interface. Connect to
Microprocessor Bus Address Bits [6:2]. HBA[6] is
the most significant bit, and HBA[2] is the least sig-
nificant bit. HBA[1] is never used in the uP Host Bus,
because all of the registers are 8-bit or 16-bit and
are aligned to 32-bit word boundaries. When
HBFIFO = 1, HBA[6:2] are ignored.
129
50
J19
PCI_PERR#
PCI_PERR#
HBWAIT#
I/O
I/
Opsts33
Opsts33
PCI_PERR#: Parity Error. PERR# is used for the
reporting of data parity errors. Connect to PCI Bus:
PERR#.
HBWAIT#: Microprocessor Bus Wait. Low active.
Connect to Microprocessor Bus Wait. HBWAIT# = 0
adds one HBCLK clock cycle to the address setup
and data access time during Burst Mode transfers;
data is transferred in 2 HBCLK cycles instead of one
HBCLK cycle. HBWAIT# does not affect the data
transfer in Non-Burst Mode.
reporting of data parity errors. Connect to PCI Bus:
PERR#.
HBWAIT#: Microprocessor Bus Wait. Low active.
Connect to Microprocessor Bus Wait. HBWAIT# = 0
adds one HBCLK clock cycle to the address setup
and data access time during Burst Mode transfers;
data is transferred in 2 HBCLK cycles instead of one
HBCLK cycle. HBWAIT# does not affect the data
transfer in Non-Burst Mode.
130
51
T19
PCI_REQ#
PCI_REQ1#
Reserved
I/O
I/
Opsts33
Opsts33
PCI_REQ1#: Request. REQ# is used to indicate to
the arbiter that this agent desires use of the bus.
Connect to PCI Bus: REQ#.
Reserved. Leave open.
the arbiter that this agent desires use of the bus.
Connect to PCI Bus: REQ#.
Reserved. Leave open.
131
52
J20
PCI_SERR#
PCI_SERR#
HBW#
I/O
I/
Opsts33
Opsts33
PCI_SERR#: System Error. SERR# is an open drain
output asserted to report address parity errors, data
parity errors on the Special Cycle command, or any
other system error where the result will be cata-
strophic. Connect to PCI Bus: SERR#.
HBW#: Microprocessor Bus Write. Low active. Con-
nect to Microprocessor Bus Write. HBW# = 0 for a
write cycle, and HBW# = 1 for a read cycle.
output asserted to report address parity errors, data
parity errors on the Special Cycle command, or any
other system error where the result will be cata-
strophic. Connect to PCI Bus: SERR#.
HBW#: Microprocessor Bus Write. Low active. Con-
nect to Microprocessor Bus Write. HBW# = 0 for a
write cycle, and HBW# = 1 for a read cycle.
Total
Signals
Interface
Signals
Pin
PCI &
µP Bus Interface Signal Name Pin Com-
patible Mode and Enhanced Feature Mode
Signal
Type
I/O Type
Signal Description
PCI Bus -
Peripheral
Mode
PCI Bus - Host
Mode
uP Bus Mode
32
KX-NCP1104XJ
132
53
K22
PCI_STOP#
PCI_STOP#
HBFIFO
I/O
I/
Opsts33
Opsts33
PCI_STOP#: Stop. STOP# is asserted to indicate
the Bus Interface is requesting the master to stop
the current transaction. Connect to PCI Bus:
STOP#.
HBFIFO: Microprocessor Bus FIFO Select. Connect
to the Microprocessor Bus Address Bit used to
select the Host Interface FIFO in the system
address space.
HBFIFO = 1, selects Host Interface FIFO (HBA[6:2]
are ignored).
HBFIFO = 0, selects Host Interface Registers (spec-
ified by HBA[6:2]).
the Bus Interface is requesting the master to stop
the current transaction. Connect to PCI Bus:
STOP#.
HBFIFO: Microprocessor Bus FIFO Select. Connect
to the Microprocessor Bus Address Bit used to
select the Host Interface FIFO in the system
address space.
HBFIFO = 1, selects Host Interface FIFO (HBA[6:2]
are ignored).
HBFIFO = 0, selects Host Interface Registers (spec-
ified by HBA[6:2]).
133
54
K20
PCI_TRDY#
PCI_TRDY#
HBCS#
I/O
I/
Opsts33
Opsts33
PCI_TRDY#: Target Ready. TRDY# is used to indi-
cate the Bus Interface’s ability to complete the cur-
rent data phase of the transaction. TRDY# is used in
conjunction with IRDY#. Connect to PCI Bus:
TRDY#.
HBCS#: Microprocessor Bus Chip Select. Low
active. Connect to Microprocessor Bus Chip Select.
cate the Bus Interface’s ability to complete the cur-
rent data phase of the transaction. TRDY# is used in
conjunction with IRDY#. Connect to PCI Bus:
TRDY#.
HBCS#: Microprocessor Bus Chip Select. Low
active. Connect to Microprocessor Bus Chip Select.
Total
Signals
Interface
Signals
Pin
Ethernet Interface Signal Name
Pin Compatible Mode and Enhanced Feature
Mode
Signal
Type
I/O Type
Signal Description
RMII Interface
Mode
S3MII
Interface
Mode
MII Interface
Mode
(Software
Selected)
Selected)
134
1
J3
RMII_Select# =
0
0
S3MII_Select
= 1
= 1
MII_COL
I
Id/Ot4
RMII_Select#, S3MII_Select: Ethernet Boot Select
0 (Low) = RMII Ethernet Boot (default, internal pull-
down)
1 (High) = S3MII Ethernet Boot
MII_COL: Collision Detected. COL shall be asserted
by the PHY when an Ethernet Frame collision is
detected on the wire. For detailed information, refer
to IEEE 802.3.
0 (Low) = RMII Ethernet Boot (default, internal pull-
down)
1 (High) = S3MII Ethernet Boot
MII_COL: Collision Detected. COL shall be asserted
by the PHY when an Ethernet Frame collision is
detected on the wire. For detailed information, refer
to IEEE 802.3.
135
2
K2
RMII_MDC
S3MII_MDC
MII_MDC
O
Ots8
RMII_MDC/S3MII_MDC/MII_MDC:Management
Data Clock. MDC is sourced by the M825xx(2) to
the PHY as the timing reference for transfer of infor-
mation on the MDIO signal. For detailed information,
refer to IEEE 802.3 section 22.
Data Clock. MDC is sourced by the M825xx(2) to
the PHY as the timing reference for transfer of infor-
mation on the MDIO signal. For detailed information,
refer to IEEE 802.3 section 22.
136
3
K3
RMII_MDIO
S3MII_MDIO
MII_MDIO
I/O
I/Ots8
RMII_MDIO/S3MII_MDIO/MII_MDIO:Management
Data I/O. MDIO is a bi-directional signal between
the PHY and the M825xx(2). For detailed informa-
tion, refer to IEEE 802.3 section 22.
Data I/O. MDIO is a bi-directional signal between
the PHY and the M825xx(2). For detailed informa-
tion, refer to IEEE 802.3 section 22.
137
4
H4
RMII_Link Sta-
tus#
tus#
Reserved
MII_CRS
I
Id/Ot4
RMII_Link Status#: Link Status 0 (Low) = Link Active
(default, internal pull-down)
1 (High) = Link Not Active
Reserved: Internal pull-down. Leave open if not
used.
MII_CRS: Carrier Sense. CRS shall be asserted by
the PHY when carrier is detected on the wire. For
detailed information, refer to IEEE 802.3.
(default, internal pull-down)
1 (High) = Link Not Active
Reserved: Internal pull-down. Leave open if not
used.
MII_CRS: Carrier Sense. CRS shall be asserted by
the PHY when carrier is detected on the wire. For
detailed information, refer to IEEE 802.3.
138
5
H1
RMII_Full
Duplex#
Duplex#
Reserved
MII_RXD2
I
Id/Ot4
RMII_ Full Duplex#: Full Duplex 0 (Low) = Full
Duplex (default, internal pull-down)
1 (High) = Half Duplex
Reserved: Internal pull-down. Leave open if not
used.
MII_RXD2: Receive Data. RXD [3:0] transition syn-
chronously with respect to the RX_CLK. RXD [3:0]
are driven by the PHY. For each RX_CLK period in
which DV is asserted, RXD [3:0] transfer four bits of
Duplex (default, internal pull-down)
1 (High) = Half Duplex
Reserved: Internal pull-down. Leave open if not
used.
MII_RXD2: Receive Data. RXD [3:0] transition syn-
chronously with respect to the RX_CLK. RXD [3:0]
are driven by the PHY. For each RX_CLK period in
which DV is asserted, RXD [3:0] transfer four bits of
recovered data from the PHY to the M825xx(2).
For detailed information, refer to IEEE 802.3 sec-
tion 22. NOTE: pin L1 does NOT have an internal
pull-down resistor.
tion 22. NOTE: pin L1 does NOT have an internal
pull-down resistor.
Total
Signals
Interface
Signals
Pin
PCI &
µP Bus Interface Signal Name Pin Com-
patible Mode and Enhanced Feature Mode
Signal
Type
I/O Type
Signal Description
PCI Bus -
Peripheral
Mode
PCI Bus - Host
Mode
uP Bus Mode
Click on the first or last page to see other KX-NCP1104XJ (serv.man2) service manuals if exist.